A Primer On Hardware Prefetching

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A Primer on Hardware Prefetching

Author : Babak Falsafi
Publisher : Springer Nature
ISBN 13 : 3031017439
Total Pages : 54 pages
Book Rating : 4.0/5 (31 download)

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Book Synopsis A Primer on Hardware Prefetching by : Babak Falsafi

Download or read book A Primer on Hardware Prefetching written by Babak Falsafi and published by Springer Nature. This book was released on 2022-06-01 with total page 54 pages. Available in PDF, EPUB and Kindle. Book excerpt: Since the 1970’s, microprocessor-based digital platforms have been riding Moore’s law, allowing for doubling of density for the same area roughly every two years. However, whereas microprocessor fabrication has focused on increasing instruction execution rate, memory fabrication technologies have focused primarily on an increase in capacity with negligible increase in speed. This divergent trend in performance between the processors and memory has led to a phenomenon referred to as the “Memory Wall.” To overcome the memory wall, designers have resorted to a hierarchy of cache memory levels, which rely on the principal of memory access locality to reduce the observed memory access time and the performance gap between processors and memory. Unfortunately, important workload classes exhibit adverse memory access patterns that baffle the simple policies built into modern cache hierarchies to move instructions and data across cache levels. As such, processors often spend much time idling upon a demand fetch of memory blocks that miss in higher cache levels. Prefetching—predicting future memory accesses and issuing requests for the corresponding memory blocks in advance of explicit accesses—is an effective approach to hide memory access latency. There have been a myriad of proposed prefetching techniques, and nearly every modern processor includes some hardware prefetching mechanisms targeting simple and regular memory access patterns. This primer offers an overview of the various classes of hardware prefetchers for instructions and data proposed in the research literature, and presents examples of techniques incorporated into modern microprocessors.

A Primer on Hardware Prefetching

Author : Babak Falsafi
Publisher : Morgan & Claypool Publishers
ISBN 13 : 1608459535
Total Pages : 69 pages
Book Rating : 4.6/5 (84 download)

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Book Synopsis A Primer on Hardware Prefetching by : Babak Falsafi

Download or read book A Primer on Hardware Prefetching written by Babak Falsafi and published by Morgan & Claypool Publishers. This book was released on 2014-05-01 with total page 69 pages. Available in PDF, EPUB and Kindle. Book excerpt: Since the 1970’s, microprocessor-based digital platforms have been riding Moore’s law, allowing for doubling of density for the same area roughly every two years. However, whereas microprocessor fabrication has focused on increasing instruction execution rate, memory fabrication technologies have focused primarily on an increase in capacity with negligible increase in speed. This divergent trend in performance between the processors and memory has led to a phenomenon referred to as the “Memory Wall.” To overcome the memory wall, designers have resorted to a hierarchy of cache memory levels, which rely on the principal of memory access locality to reduce the observed memory access time and the performance gap between processors and memory. Unfortunately, important workload classes exhibit adverse memory access patterns that baffle the simple policies built into modern cache hierarchies to move instructions and data across cache levels. As such, processors often spend much time idling upon a demand fetch of memory blocks that miss in higher cache levels. Prefetching—predicting future memory accesses and issuing requests for the corresponding memory blocks in advance of explicit accesses—is an effective approach to hide memory access latency. There have been a myriad of proposed prefetching techniques, and nearly every modern processor includes some hardware prefetching mechanisms targeting simple and regular memory access patterns. This primer offers an overview of the various classes of hardware prefetchers for instructions and data proposed in the research literature, and presents examples of techniques incorporated into modern microprocessors.

A Primer on Memory Persistency

Author : Gogte Vaibhav
Publisher : Springer Nature
ISBN 13 : 303179205X
Total Pages : 95 pages
Book Rating : 4.0/5 (317 download)

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Book Synopsis A Primer on Memory Persistency by : Gogte Vaibhav

Download or read book A Primer on Memory Persistency written by Gogte Vaibhav and published by Springer Nature. This book was released on 2022-06-01 with total page 95 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book introduces readers to emerging persistent memory (PM) technologies that promise the performance of dynamic random-access memory (DRAM) with the durability of traditional storage media, such as hard disks and solid-state drives (SSDs). Persistent memories (PMs), such as Intel's Optane DC persistent memories, are commercially available today. Unlike traditional storage devices, PMs can be accessed over a byte-addressable load-store interface with access latency that is comparable to DRAM. Unfortunately, existing hardware and software systems are ill-equipped to fully avail the potential of these byte-addressable memory technologies as they have been designed to access traditional storage media over a block-based interface. Several mechanisms have been explored in the research literature over the past decade to design hardware and software systems that provide high-performance access to PMs.Because PMs are durable, they can retain data across failures, such as power failures and program crashes. Upon a failure, recovery mechanisms may inspect PM data, reconstruct state and resume program execution. Correct recovery of data requires that operations to the PM are properly ordered during normal program execution. Memory persistency models define the order in which memory operations are performed at the PM. Much like memory consistency models, memory persistency models may be relaxed to improve application performance. Several proposals have emerged recently to design memory persistency models for hardware and software systems and for high-level programming languages. These proposals differ in several key aspects; they relax PM ordering constraints, introduce varying programmability burden, and introduce differing granularity of failure atomicity for PM operations.This primer provides a detailed overview of the various classes of the memory persistency models, their implementations in hardware, programming languages and software systems proposed in the recent research literature, and the PM ordering techniques employed by modern processors.

A Primer on Memory Consistency and Cache Coherence, Second Edition

Author : Vijay Nagarajan
Publisher : Springer Nature
ISBN 13 : 3031017641
Total Pages : 276 pages
Book Rating : 4.0/5 (31 download)

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Book Synopsis A Primer on Memory Consistency and Cache Coherence, Second Edition by : Vijay Nagarajan

Download or read book A Primer on Memory Consistency and Cache Coherence, Second Edition written by Vijay Nagarajan and published by Springer Nature. This book was released on 2022-05-31 with total page 276 pages. Available in PDF, EPUB and Kindle. Book excerpt: Many modern computer systems, including homogeneous and heterogeneous architectures, support shared memory in hardware. In a shared memory system, each of the processor cores may read and write to a single shared address space. For a shared memory machine, the memory consistency model defines the architecturally visible behavior of its memory system. Consistency definitions provide rules about loads and stores (or memory reads and writes) and how they act upon memory. As part of supporting a memory consistency model, many machines also provide cache coherence protocols that ensure that multiple cached copies of data are kept up-to-date. The goal of this primer is to provide readers with a basic understanding of consistency and coherence. This understanding includes both the issues that must be solved as well as a variety of solutions. We present both high-level concepts as well as specific, concrete examples from real-world systems. This second edition reflects a decade of advancements since the first edition and includes, among other more modest changes, two new chapters: one on consistency and coherence for non-CPU accelerators (with a focus on GPUs) and one that points to formal work and tools on consistency and coherence.

A Primer on Compression in the Memory Hierarchy

Author : Somayeh Sardashti
Publisher : Springer Nature
ISBN 13 : 303101751X
Total Pages : 70 pages
Book Rating : 4.0/5 (31 download)

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Book Synopsis A Primer on Compression in the Memory Hierarchy by : Somayeh Sardashti

Download or read book A Primer on Compression in the Memory Hierarchy written by Somayeh Sardashti and published by Springer Nature. This book was released on 2022-05-31 with total page 70 pages. Available in PDF, EPUB and Kindle. Book excerpt: This synthesis lecture presents the current state-of-the-art in applying low-latency, lossless hardware compression algorithms to cache, memory, and the memory/cache link. There are many non-trivial challenges that must be addressed to make data compression work well in this context. First, since compressed data must be decompressed before it can be accessed, decompression latency ends up on the critical memory access path. This imposes a significant constraint on the choice of compression algorithms. Second, while conventional memory systems store fixed-size entities like data types, cache blocks, and memory pages, these entities will suddenly vary in size in a memory system that employs compression. Dealing with variable size entities in a memory system using compression has a significant impact on the way caches are organized and how to manage the resources in main memory. We systematically discuss solutions in the open literature to these problems. Chapter 2 provides the foundations of data compression by first introducing the fundamental concept of value locality. We then introduce a taxonomy of compression algorithms and show how previously proposed algorithms fit within that logical framework. Chapter 3 discusses the different ways that cache memory systems can employ compression, focusing on the trade-offs between latency, capacity, and complexity of alternative ways to compact compressed cache blocks. Chapter 4 discusses issues in applying data compression to main memory and Chapter 5 covers techniques for compressing data on the cache-to-memory links. This book should help a skilled memory system designer understand the fundamental challenges in applying compression to the memory hierarchy and introduce him/her to the state-of-the-art techniques in addressing them.

Research Infrastructures for Hardware Accelerators

Author : Yakun Sophia Shao
Publisher : Springer Nature
ISBN 13 : 3031017501
Total Pages : 85 pages
Book Rating : 4.0/5 (31 download)

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Book Synopsis Research Infrastructures for Hardware Accelerators by : Yakun Sophia Shao

Download or read book Research Infrastructures for Hardware Accelerators written by Yakun Sophia Shao and published by Springer Nature. This book was released on 2022-05-31 with total page 85 pages. Available in PDF, EPUB and Kindle. Book excerpt: Hardware acceleration in the form of customized datapath and control circuitry tuned to specific applications has gained popularity for its promise to utilize transistors more efficiently. Historically, the computer architecture community has focused on general-purpose processors, and extensive research infrastructure has been developed to support research efforts in this domain. Envisioning future computing systems with a diverse set of general-purpose cores and accelerators, computer architects must add accelerator-related research infrastructures to their toolboxes to explore future heterogeneous systems. This book serves as a primer for the field, as an overview of the vast literature on accelerator architectures and their design flows, and as a resource guidebook for researchers working in related areas.

Hardware and Software Support for Virtualization

Author : Edouard Bugnion
Publisher : Springer Nature
ISBN 13 : 3031017536
Total Pages : 188 pages
Book Rating : 4.0/5 (31 download)

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Book Synopsis Hardware and Software Support for Virtualization by : Edouard Bugnion

Download or read book Hardware and Software Support for Virtualization written by Edouard Bugnion and published by Springer Nature. This book was released on 2022-06-01 with total page 188 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book focuses on the core question of the necessary architectural support provided by hardware to efficiently run virtual machines, and of the corresponding design of the hypervisors that run them. Virtualization is still possible when the instruction set architecture lacks such support, but the hypervisor remains more complex and must rely on additional techniques. Despite the focus on architectural support in current architectures, some historical perspective is necessary to appropriately frame the problem. The first half of the book provides the historical perspective of the theoretical framework developed four decades ago by Popek and Goldberg. It also describes earlier systems that enabled virtualization despite the lack of architectural support in hardware. As is often the case, theory defines a necessary—but not sufficient—set of features, and modern architectures are the result of the combination of the theoretical framework with insights derived from practical systems. The second half of the book describes state-of-the-art support for virtualization in both x86-64 and ARM processors. This book includes an in-depth description of the CPU, memory, and I/O virtualization of these two processor architectures, as well as case studies on the Linux/KVM, VMware, and Xen hypervisors. It concludes with a performance comparison of virtualization on current-generation x86- and ARM-based systems across multiple hypervisors.

iRODS Primer 2

Author : Yu-Ting Chen
Publisher : Morgan & Claypool Publishers
ISBN 13 : 1627059725
Total Pages : 159 pages
Book Rating : 4.6/5 (27 download)

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Book Synopsis iRODS Primer 2 by : Yu-Ting Chen

Download or read book iRODS Primer 2 written by Yu-Ting Chen and published by Morgan & Claypool Publishers. This book was released on 2015-07-01 with total page 159 pages. Available in PDF, EPUB and Kindle. Book excerpt: Since the end of Dennard scaling in the early 2000s, improving the energy efficiency of computation has been the main concern of the research community and industry. The large energy efficiency gap between general-purpose processors and application-specific integrated circuits (ASICs) motivates the exploration of customizable architectures, where one can adapt the architecture to the workload. In this Synthesis lecture, we present an overview and introduction of the recent developments on energy-efficient customizable architectures, including customizable cores and accelerators, on-chip memory customization, and interconnect optimization. In addition to a discussion of the general techniques and classification of different approaches used in each area, we also highlight and illustrate some of the most successful design examples in each category and discuss their impact on performance and energy efficiency. We hope that this work captures the state-of-the-art research and development on customizable architectures and serves as a useful reference basis for further research, design, and implementation for large-scale deployment in future computing systems.

Robotic Computing on FPGAs

Author : Shaoshan Liu
Publisher : Springer Nature
ISBN 13 : 3031017714
Total Pages : 202 pages
Book Rating : 4.0/5 (31 download)

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Book Synopsis Robotic Computing on FPGAs by : Shaoshan Liu

Download or read book Robotic Computing on FPGAs written by Shaoshan Liu and published by Springer Nature. This book was released on 2022-05-31 with total page 202 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book provides a thorough overview of the state-of-the-art field-programmable gate array (FPGA)-based robotic computing accelerator designs and summarizes their adopted optimized techniques. This book consists of ten chapters, delving into the details of how FPGAs have been utilized in robotic perception, localization, planning, and multi-robot collaboration tasks. In addition to individual robotic tasks, this book provides detailed descriptions of how FPGAs have been used in robotic products, including commercial autonomous vehicles and space exploration robots.

AI for Computer Architecture

Author : Lizhong Chen
Publisher : Springer Nature
ISBN 13 : 3031017706
Total Pages : 124 pages
Book Rating : 4.0/5 (31 download)

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Book Synopsis AI for Computer Architecture by : Lizhong Chen

Download or read book AI for Computer Architecture written by Lizhong Chen and published by Springer Nature. This book was released on 2022-05-31 with total page 124 pages. Available in PDF, EPUB and Kindle. Book excerpt: Artificial intelligence has already enabled pivotal advances in diverse fields, yet its impact on computer architecture has only just begun. In particular, recent work has explored broader application to the design, optimization, and simulation of computer architecture. Notably, machine-learning-based strategies often surpass prior state-of-the-art analytical, heuristic, and human-expert approaches. This book reviews the application of machine learning in system-wide simulation and run-time optimization, and in many individual components such as caches/memories, branch predictors, networks-on-chip, and GPUs. The book further analyzes current practice to highlight useful design strategies and identify areas for future work, based on optimized implementation strategies, opportune extensions to existing work, and ambitious long term possibilities. Taken together, these strategies and techniques present a promising future for increasingly automated computer architecture designs.

General-Purpose Graphics Processor Architectures

Author : Tor M. Aamodt
Publisher : Springer Nature
ISBN 13 : 3031017595
Total Pages : 122 pages
Book Rating : 4.0/5 (31 download)

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Book Synopsis General-Purpose Graphics Processor Architectures by : Tor M. Aamodt

Download or read book General-Purpose Graphics Processor Architectures written by Tor M. Aamodt and published by Springer Nature. This book was released on 2022-05-31 with total page 122 pages. Available in PDF, EPUB and Kindle. Book excerpt: Originally developed to support video games, graphics processor units (GPUs) are now increasingly used for general-purpose (non-graphics) applications ranging from machine learning to mining of cryptographic currencies. GPUs can achieve improved performance and efficiency versus central processing units (CPUs) by dedicating a larger fraction of hardware resources to computation. In addition, their general-purpose programmability makes contemporary GPUs appealing to software developers in comparison to domain-specific accelerators. This book provides an introduction to those interested in studying the architecture of GPUs that support general-purpose computing. It collects together information currently only found among a wide range of disparate sources. The authors led development of the GPGPU-Sim simulator widely used in academic research on GPU architectures. The first chapter of this book describes the basic hardware structure of GPUs and provides a brief overview of their history. Chapter 2 provides a summary of GPU programming models relevant to the rest of the book. Chapter 3 explores the architecture of GPU compute cores. Chapter 4 explores the architecture of the GPU memory system. After describing the architecture of existing systems, Chapters 3 and 4 provide an overview of related research. Chapter 5 summarizes cross-cutting research impacting both the compute core and memory system. This book should provide a valuable resource for those wishing to understand the architecture of graphics processor units (GPUs) used for acceleration of general-purpose applications and to those who want to obtain an introduction to the rapidly growing body of research exploring how to improve the architecture of these GPUs.

Principles of Secure Processor Architecture Design

Author : Jakub Szefer
Publisher : Springer Nature
ISBN 13 : 3031017609
Total Pages : 154 pages
Book Rating : 4.0/5 (31 download)

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Book Synopsis Principles of Secure Processor Architecture Design by : Jakub Szefer

Download or read book Principles of Secure Processor Architecture Design written by Jakub Szefer and published by Springer Nature. This book was released on 2022-06-01 with total page 154 pages. Available in PDF, EPUB and Kindle. Book excerpt: With growing interest in computer security and the protection of the code and data which execute on commodity computers, the amount of hardware security features in today's processors has increased significantly over the recent years. No longer of just academic interest, security features inside processors have been embraced by industry as well, with a number of commercial secure processor architectures available today. This book aims to give readers insights into the principles behind the design of academic and commercial secure processor architectures. Secure processor architecture research is concerned with exploring and designing hardware features inside computer processors, features which can help protect confidentiality and integrity of the code and data executing on the processor. Unlike traditional processor architecture research that focuses on performance, efficiency, and energy as the first-order design objectives, secure processor architecture design has security as the first-order design objective (while still keeping the others as important design aspects that need to be considered). This book aims to present the different challenges of secure processor architecture design to graduate students interested in research on architecture and hardware security and computer architects working in industry interested in adding security features to their designs. It aims to educate readers about how the different challenges have been solved in the past and what are the best practices, i.e., the principles, for design of new secure processor architectures. Based on the careful review of past work by many computer architects and security researchers, readers also will come to know the five basic principles needed for secure processor architecture design. The book also presents existing research challenges and potential new research directions. Finally, this book presents numerous design suggestions, as well as discusses pitfalls and fallacies that designers should avoid.

Deep Learning Systems

Author : Andres Rodriguez
Publisher : Springer Nature
ISBN 13 : 3031017692
Total Pages : 245 pages
Book Rating : 4.0/5 (31 download)

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Book Synopsis Deep Learning Systems by : Andres Rodriguez

Download or read book Deep Learning Systems written by Andres Rodriguez and published by Springer Nature. This book was released on 2022-05-31 with total page 245 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book describes deep learning systems: the algorithms, compilers, and processor components to efficiently train and deploy deep learning models for commercial applications. The exponential growth in computational power is slowing at a time when the amount of compute consumed by state-of-the-art deep learning (DL) workloads is rapidly growing. Model size, serving latency, and power constraints are a significant challenge in the deployment of DL models for many applications. Therefore, it is imperative to codesign algorithms, compilers, and hardware to accelerate advances in this field with holistic system-level and algorithm solutions that improve performance, power, and efficiency. Advancing DL systems generally involves three types of engineers: (1) data scientists that utilize and develop DL algorithms in partnership with domain experts, such as medical, economic, or climate scientists; (2) hardware designers that develop specialized hardware to accelerate the components in the DL models; and (3) performance and compiler engineers that optimize software to run more efficiently on a given hardware. Hardware engineers should be aware of the characteristics and components of production and academic models likely to be adopted by industry to guide design decisions impacting future hardware. Data scientists should be aware of deployment platform constraints when designing models. Performance engineers should support optimizations across diverse models, libraries, and hardware targets. The purpose of this book is to provide a solid understanding of (1) the design, training, and applications of DL algorithms in industry; (2) the compiler techniques to map deep learning code to hardware targets; and (3) the critical hardware features that accelerate DL systems. This book aims to facilitate co-innovation for the advancement of DL systems. It is written for engineers working in one or more of these areas who seek to understand the entire system stack in order to better collaborate with engineers working in other parts of the system stack. The book details advancements and adoption of DL models in industry, explains the training and deployment process, describes the essential hardware architectural features needed for today's and future models, and details advances in DL compilers to efficiently execute algorithms across various hardware targets. Unique in this book is the holistic exposition of the entire DL system stack, the emphasis on commercial applications, and the practical techniques to design models and accelerate their performance. The author is fortunate to work with hardware, software, data scientist, and research teams across many high-technology companies with hyperscale data centers. These companies employ many of the examples and methods provided throughout the book.

Compiling Algorithms for Heterogeneous Systems

Author : Steven Bell
Publisher : Springer Nature
ISBN 13 : 3031017587
Total Pages : 89 pages
Book Rating : 4.0/5 (31 download)

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Book Synopsis Compiling Algorithms for Heterogeneous Systems by : Steven Bell

Download or read book Compiling Algorithms for Heterogeneous Systems written by Steven Bell and published by Springer Nature. This book was released on 2022-05-31 with total page 89 pages. Available in PDF, EPUB and Kindle. Book excerpt: Most emerging applications in imaging and machine learning must perform immense amounts of computation while holding to strict limits on energy and power. To meet these goals, architects are building increasingly specialized compute engines tailored for these specific tasks. The resulting computer systems are heterogeneous, containing multiple processing cores with wildly different execution models. Unfortunately, the cost of producing this specialized hardware—and the software to control it—is astronomical. Moreover, the task of porting algorithms to these heterogeneous machines typically requires that the algorithm be partitioned across the machine and rewritten for each specific architecture, which is time consuming and prone to error. Over the last several years, the authors have approached this problem using domain-specific languages (DSLs): high-level programming languages customized for specific domains, such as database manipulation, machine learning, or image processing. By giving up generality, these languages are able to provide high-level abstractions to the developer while producing high-performance output. The purpose of this book is to spur the adoption and the creation of domain-specific languages, especially for the task of creating hardware designs. In the first chapter, a short historical journey explains the forces driving computer architecture today. Chapter 2 describes the various methods for producing designs for accelerators, outlining the push for more abstraction and the tools that enable designers to work at a higher conceptual level. From there, Chapter 3 provides a brief introduction to image processing algorithms and hardware design patterns for implementing them. Chapters 4 and 5 describe and compare Darkroom and Halide, two domain-specific languages created for image processing that produce high-performance designs for both FPGAs and CPUs from the same source code, enabling rapid design cycles and quick porting of algorithms. The final section describes how the DSL approach also simplifies the problem of interfacing between application code and the accelerator by generating the driver stack in addition to the accelerator configuration. This book should serve as a useful introduction to domain-specialized computing for computer architecture students and as a primer on domain-specific languages and image processing hardware for those with more experience in the field.

Architectural and Operating System Support for Virtual Memory

Author : Abhishek Bhattacharjee
Publisher : Springer Nature
ISBN 13 : 3031017579
Total Pages : 168 pages
Book Rating : 4.0/5 (31 download)

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Book Synopsis Architectural and Operating System Support for Virtual Memory by : Abhishek Bhattacharjee

Download or read book Architectural and Operating System Support for Virtual Memory written by Abhishek Bhattacharjee and published by Springer Nature. This book was released on 2022-05-31 with total page 168 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book provides computer engineers, academic researchers, new graduate students, and seasoned practitioners an end-to-end overview of virtual memory. We begin with a recap of foundational concepts and discuss not only state-of-the-art virtual memory hardware and software support available today, but also emerging research trends in this space. The span of topics covers processor microarchitecture, memory systems, operating system design, and memory allocation. We show how efficient virtual memory implementations hinge on careful hardware and software cooperation, and we discuss new research directions aimed at addressing emerging problems in this space. Virtual memory is a classic computer science abstraction and one of the pillars of the computing revolution. It has long enabled hardware flexibility, software portability, and overall better security, to name just a few of its powerful benefits. Nearly all user-level programs today take for granted that they will have been freed from the burden of physical memory management by the hardware, the operating system, device drivers, and system libraries. However, despite its ubiquity in systems ranging from warehouse-scale datacenters to embedded Internet of Things (IoT) devices, the overheads of virtual memory are becoming a critical performance bottleneck today. Virtual memory architectures designed for individual CPUs or even individual cores are in many cases struggling to scale up and scale out to today's systems which now increasingly include exotic hardware accelerators (such as GPUs, FPGAs, or DSPs) and emerging memory technologies (such as non-volatile memory), and which run increasingly intensive workloads (such as virtualized and/or "big data" applications). As such, many of the fundamental abstractions and implementation approaches for virtual memory are being augmented, extended, or entirely rebuilt in order to ensure that virtual memory remains viable and performant in the years to come.

Parallel Processing, 1980 to 2020

Author : Robert Kuhn
Publisher : Springer Nature
ISBN 13 : 3031017684
Total Pages : 166 pages
Book Rating : 4.0/5 (31 download)

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Book Synopsis Parallel Processing, 1980 to 2020 by : Robert Kuhn

Download or read book Parallel Processing, 1980 to 2020 written by Robert Kuhn and published by Springer Nature. This book was released on 2022-05-31 with total page 166 pages. Available in PDF, EPUB and Kindle. Book excerpt: This historical survey of parallel processing from 1980 to 2020 is a follow-up to the authors’ 1981 Tutorial on Parallel Processing, which covered the state of the art in hardware, programming languages, and applications. Here, we cover the evolution of the field since 1980 in: parallel computers, ranging from the Cyber 205 to clusters now approaching an exaflop, to multicore microprocessors, and Graphic Processing Units (GPUs) in commodity personal devices; parallel programming notations such as OpenMP, MPI message passing, and CUDA streaming notation; and seven parallel applications, such as finite element analysis and computer vision. Some things that looked like they would be major trends in 1981, such as big Single Instruction Multiple Data arrays disappeared for some time but have been revived recently in deep neural network processors. There are now major trends that did not exist in 1980, such as GPUs, distributed memory machines, and parallel processing in nearly every commodity device. This book is intended for those that already have some knowledge of parallel processing today and want to learn about the history of the three areas. In parallel hardware, every major parallel architecture type from 1980 has scaled-up in performance and scaled-out into commodity microprocessors and GPUs, so that every personal and embedded device is a parallel processor. There has been a confluence of parallel architecture types into hybrid parallel systems. Much of the impetus for change has been Moore’s Law, but as clock speed increases have stopped and feature size decreases have slowed down, there has been increased demand on parallel processing to continue performance gains. In programming notations and compilers, we observe that the roots of today’s programming notations existed before 1980. And that, through a great deal of research, the most widely used programming notations today, although the result of much broadening of these roots, remain close to target system architectures allowing the programmer to almost explicitly use the target’s parallelism to the best of their ability. The parallel versions of applications directly or indirectly impact nearly everyone, computer expert or not, and parallelism has brought about major breakthroughs in numerous application areas. Seven parallel applications are studied in this book.

A Primer on Memory Consistency and Cache Coherence

Author : Daniel Sorin
Publisher : Springer Nature
ISBN 13 : 3031017331
Total Pages : 206 pages
Book Rating : 4.0/5 (31 download)

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Book Synopsis A Primer on Memory Consistency and Cache Coherence by : Daniel Sorin

Download or read book A Primer on Memory Consistency and Cache Coherence written by Daniel Sorin and published by Springer Nature. This book was released on 2011-05-10 with total page 206 pages. Available in PDF, EPUB and Kindle. Book excerpt: Many modern computer systems and most multicore chips (chip multiprocessors) support shared memory in hardware. In a shared memory system, each of the processor cores may read and write to a single shared address space. For a shared memory machine, the memory consistency model defines the architecturally visible behavior of its memory system. Consistency definitions provide rules about loads and stores (or memory reads and writes) and how they act upon memory. As part of supporting a memory consistency model, many machines also provide cache coherence protocols that ensure that multiple cached copies of data are kept up-to-date. The goal of this primer is to provide readers with a basic understanding of consistency and coherence. This understanding includes both the issues that must be solved as well as a variety of solutions. We present both highlevel concepts as well as specific, concrete examples from real-world systems. Table of Contents: Preface / Introduction to Consistency and Coherence / Coherence Basics / Memory Consistency Motivation and Sequential Consistency / Total Store Order and the x86 Memory Model / Relaxed Memory Consistency / Coherence Protocols / Snooping Coherence Protocols / Directory Coherence Protocols / Advanced Topics in Coherence / Author Biographies