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Design Of A High Speed Folding And Interpolation Analog To Digital Converter Implemented In 018 Micrometer Silicon Germanide Bicmos Process
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Book Synopsis Design of a High Speed Folding and Interpolation Analog to Digital Converter Implemented in 0.18 Micrometer Silicon Germanide BiCMOS Process by : Quincy Kwan-Lun Fung
Download or read book Design of a High Speed Folding and Interpolation Analog to Digital Converter Implemented in 0.18 Micrometer Silicon Germanide BiCMOS Process written by Quincy Kwan-Lun Fung and published by . This book was released on 2008 with total page 194 pages. Available in PDF, EPUB and Kindle. Book excerpt: This thesis describes the design and implementation of an 8 bit, 2 GSamples/s analog to digital converter for a 0.18 mum SiGe BiCMOS process with a unity gain cut off frequency of 60 GHz. This folding and interpolation ADC consists of a highly linear track-and-hold amplifier (THA) with 10 bit resolution, a differential resistor ladder, four folding amplifiers, an interpolation stage, a comparator array, a digital encoder with bubble error correction scheme and a coarse quantizer. The microchip area is 3.0 x 3.4 mm2 including pads and buffer circuits. Simulation results show that this ADC has a maximum signal-to-noise and distortion ratio (SNDR) of 48.9 dB corresponding to a 7.5 effective number of bits (ENOB) and an effective resolution bandwidth (ERBW) of 700MHz. The circuit demonstrates a maximum differential nonlinearity (DNL) and integral nonlinearity (INL) of 0.4 and 0.8 LSB, respectively while consuming 3.1W from a single 3.5 V supply.
Book Synopsis Design of a High Speed Folding and Interpolation Analog to Digital Converter Implemented in 0.18 Um SiGe BiCMOS Process by : Quincy K. L. Fung
Download or read book Design of a High Speed Folding and Interpolation Analog to Digital Converter Implemented in 0.18 Um SiGe BiCMOS Process written by Quincy K. L. Fung and published by . This book was released on 2008 with total page 194 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis An 8-Bit, 1-Gsample/s Folding-Interpolating Analog-to-Digital Converter by : Wei An
Download or read book An 8-Bit, 1-Gsample/s Folding-Interpolating Analog-to-Digital Converter written by Wei An and published by . This book was released on 2000 with total page 0 pages. Available in PDF, EPUB and Kindle. Book excerpt: This thesis deals with the design and implementation of an 8-bit, 1-Gsample/s folding-interpolating analog-to-digital converter using a conventional 0.5 [mu]m self-aligned, double polysilicon bipolar process with maximum unity gain cutoff frequency fT of 25GHz. The high-speed and high-resolution A/D converter has applications in direct IF sampling receivers for wideband communications systems. The folding-interpolating architecture offers an optimum solution for Gsample/s, high-resolution A/D converters in terms of system complexity, power dissipation and chip area. The use of a silicon bipolar process allows the integration of Gsample/s ADCs with DSP systems usually realized by silicon CMOS or BiCMOS processes. The 8-bit, 1-Gsample/s A/D converter consists of a reference ladder; four folding blocks for the fine quantizer and one folding block for the coarse quantizer; interpolation resistive strings; a comparator array; a digital encoder including an EXOR array, an error-correction stage, and a 31-to-5 OR ROM; and a coarse quantizer. All circuit blocks are integrated on one chip. The chip area of the circuitry is 2.5mm x 3.5mm including bonding pads. The converter exhibits a better than 7-bit ENOB with an input signal frequency of 200MHz and at a sampling rate of 1-Gsample/s The maximum power dissipation of the ADC is 2.5W using a 5-V power supply.
Book Synopsis Design of High Speed Folding and Interpolating Analog-to-digital Converter by : Yunchu Li
Download or read book Design of High Speed Folding and Interpolating Analog-to-digital Converter written by Yunchu Li and published by . This book was released on 2004 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: High-speed and low resolution analog-to-digital converters (ADC) are key elements in the read channel of optical and magnetic data storage systems. The required resolution is about 6-7 bits while the sampling rate and effective resolution bandwidth requirements increase with each generation of storage system. Folding is a technique to reduce the number of comparators used in the flash architecture. By means of an analog preprocessing circuit in folding A/D converters the number of comparators can be reduced significantly. Folding architectures exhibit low power and low latency as well as the ability to run at high sampling rates. Folding ADCs employing interpolation schemes to generate extra folding waveforms are called "Folding and Interpolating ADC" (F & I ADC). The aim of this research is to increase the input bandwidth of high speed conversion, and low latency F & I ADC. Behavioral models are developed to analyze the bandwidth limitation at the architecture level. A front-end sample-and-hold unit is employed to tackle the frequency multiplication problem, which is intrinsic for all F & I ADCs. Current-mode signal processing is adopted to increase the bandwidth of the folding amplifiers and interpolators, which are the bottleneck of the whole system. An operational transconductance amplifier (OTA) based folding amplifier, current mirror-based interpolator, very low impedance fast current comparator are proposed and designed to carry out the current-mode signal processing. A new bit synchronization scheme is proposed to correct the error caused by the delay difference between the coarse and fine channels. A prototype chip was designed and fabricated in 0.35 ơm CMOS process to verify the ideas. The S/H and F & I ADC prototype is realized in 0.35 [mu]m double-poly CMOS process (only one poly is used). Integral nonlinearity (INL) is 1.0 LSB and Differential nonlinearity (DNL) is 0.6 LSB at 110 KHz. The ADC occupies 1.2mm2 active area and dissipates 200mW (excluding 70mW of S/H) from 3.3V supply. At 300MSPS sampling rate, the ADC achieves no less than 6 ENOB with input signal lower than 60MHz. It has the highest input bandwidth of 60MHz reported in the literature for this type of CMOS ADC with similar resolution and sample rate.
Book Synopsis An 8-bit, 12.5GS/s Folding-interpolating Analog-to-digital Converter by : Shohreh Ghetmiri
Download or read book An 8-bit, 12.5GS/s Folding-interpolating Analog-to-digital Converter written by Shohreh Ghetmiri and published by . This book was released on 2009 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis A High-speed Cascaded Folding and Interpolating A/D Converter by : Yanlok Charlotte Lau
Download or read book A High-speed Cascaded Folding and Interpolating A/D Converter written by Yanlok Charlotte Lau and published by . This book was released on 2003 with total page 86 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis Design of a High Speed Analog-to-digital Converter by : Robert James Sherwood
Download or read book Design of a High Speed Analog-to-digital Converter written by Robert James Sherwood and published by . This book was released on 1970 with total page 186 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis Low-Power High-Resolution Analog to Digital Converters by : Amir Zjajo
Download or read book Low-Power High-Resolution Analog to Digital Converters written by Amir Zjajo and published by Springer. This book was released on 2011-08-17 with total page 250 pages. Available in PDF, EPUB and Kindle. Book excerpt: With the fast advancement of CMOS fabrication technology, more and more signal-processing functions are implemented in the digital domain for a lower cost, lower power consumption, higher yield, and higher re-configurability. This has recently generated a great demand for low-power, low-voltage A/D converters that can be realized in a mainstream deep-submicron CMOS technology. However, the discrepancies between lithography wavelengths and circuit feature sizes are increasing. Lower power supply voltages significantly reduce noise margins and increase variations in process, device and design parameters. Consequently, it is steadily more difficult to control the fabrication process precisely enough to maintain uniformity. The inherent randomness of materials used in fabrication at nanoscopic scales means that performance will be increasingly variable, not only from die-to-die but also within each individual die. Parametric variability will be compounded by degradation in nanoscale integrated circuits resulting in instability of parameters over time, eventually leading to the development of faults. Process variation cannot be solved by improving manufacturing tolerances; variability must be reduced by new device technology or managed by design in order for scaling to continue. Similarly, within-die performance variation also imposes new challenges for test methods. In an attempt to address these issues, Low-Power High-Resolution Analog-to-Digital Converters specifically focus on: i) improving the power efficiency for the high-speed, and low spurious spectral A/D conversion performance by exploring the potential of low-voltage analog design and calibration techniques, respectively, and ii) development of circuit techniques and algorithms to enhance testing and debugging potential to detect errors dynamically, to isolate and confine faults, and to recover errors continuously. The feasibility of the described methods has been verified by measurements from the silicon prototypes fabricated in standard 180nm, 90nm and 65nm CMOS technology.
Book Synopsis Design of Folding and Interpolation Stages for a 1-GSample/s, 10-bit A/D Converter in SiGe BiCMOS Technology by : Chih-Yi Kuan
Download or read book Design of Folding and Interpolation Stages for a 1-GSample/s, 10-bit A/D Converter in SiGe BiCMOS Technology written by Chih-Yi Kuan and published by . This book was released on 2006 with total page 108 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis A High-speed, Folding, Analog-to-digital Converter by : Paul Louis Mangione
Download or read book A High-speed, Folding, Analog-to-digital Converter written by Paul Louis Mangione and published by . This book was released on 1994 with total page 200 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis Design of a CMOS 6-bit Folding and Interpolating Analog to Digital Converter by : Song Liu
Download or read book Design of a CMOS 6-bit Folding and Interpolating Analog to Digital Converter written by Song Liu and published by . This book was released on 1999 with total page 56 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis A High-speed, Low-power Analog-to-digital Converter in Fully Depleted Silicon-on-insulator Technology by : Kent Howard Lundberg
Download or read book A High-speed, Low-power Analog-to-digital Converter in Fully Depleted Silicon-on-insulator Technology written by Kent Howard Lundberg and published by . This book was released on 2002 with total page 200 pages. Available in PDF, EPUB and Kindle. Book excerpt: This thesis demonstrates a one-volt, high-speed, ultra-low-power, six-bit flash analog-to-digital converter fabricated in a fully depleted silicon-on-insulator CMOS technology. Silicon-on-insulator CMOS technology provides a number of benefits for low-power low-voltage analog design. The full dielectric isolation of the silicon island, where the transistors are built, allows higher layout packing density and reduces parasitic junction capacitances. Fully depleted silicon-on-insulator (SOI) exhibits improved subthreshold slope, which allows for lower transistor threshold voltages. Significant savings in power consumption can be obtained by leveraging these advantages. However, the floating-body effect can create significant problems in analog circuits, leading to potential circuit malfunction. A single-ended auto-zeroed comparator topology is optimized to leverage the advantages of fully depleted SOI technology and avoid the floating-body effect. Using this comparator topology and other circuit techniques that operate with a one-volt supply, a six-bit 500-MS/s flash A/D converter is designed with the lowest power-consumption figure of merit in its class. Consuming only 32 mA from a one-volt supply, the quantization energy figure of merit for this design is calculated to be EQ = 2 pJ. Test chips were fabricated in MIT Lincoln Laboratory's 0.25 [mu]m fully depleted SOI CMOS process. Testing of this design demonstrates the potential of SOI technology for the production of high-speed, low-power analog-to-digital converters.
Book Synopsis Design Features of a Transistorized, High Speed Analog-to-digital Converter. by : Wade E Clarke
Download or read book Design Features of a Transistorized, High Speed Analog-to-digital Converter. written by Wade E Clarke and published by Hassell Street Press. This book was released on 2023-07-18 with total page 0 pages. Available in PDF, EPUB and Kindle. Book excerpt: Design Features of a Transistorized High Speed Analog-to-Digital Converter is a technical report that describes the design of a high-speed electronic device. The report includes detailed information on the circuitry and components used in the device, as well as performance data and design considerations. This work has been selected by scholars as being culturally important, and is part of the knowledge base of civilization as we know it. This work is in the "public domain in the United States of America, and possibly other nations. Within the United States, you may freely copy and distribute this work, as no entity (individual or corporate) has a copyright on the body of the work. Scholars believe, and we concur, that this work is important enough to be preserved, reproduced, and made generally available to the public. We appreciate your support of the preservation process, and thank you for being an important part of keeping this knowledge alive and relevant.
Book Synopsis 1-Gs/s, 12-Bit High-Performance Silicon-Germanium BiCMOS Digital-to-Analog Converter by :
Download or read book 1-Gs/s, 12-Bit High-Performance Silicon-Germanium BiCMOS Digital-to-Analog Converter written by and published by . This book was released on 2002 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis A 200 MHx 6-bit Folding and Interpolating Analog to Digital Converter in 0.5-[mu] M CMOS by : Xicheng Jiang
Download or read book A 200 MHx 6-bit Folding and Interpolating Analog to Digital Converter in 0.5-[mu] M CMOS written by Xicheng Jiang and published by . This book was released on 1997 with total page 126 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis Aspects of Designing a High Speed Analog to Digital Converter by : Ming Shau Hsu
Download or read book Aspects of Designing a High Speed Analog to Digital Converter written by Ming Shau Hsu and published by . This book was released on 1992 with total page 446 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis Design Techniques for Ultra-High-Speed Time-Interleaved Analog-to-Digital Converters by : Yida Duan
Download or read book Design Techniques for Ultra-High-Speed Time-Interleaved Analog-to-Digital Converters written by Yida Duan and published by . This book was released on 2015 with total page 80 pages. Available in PDF, EPUB and Kindle. Book excerpt: Analog-to-Digital Converters (ADCs) serve as the interfaces between the analog natural world and the binary world of computer data. Due to this essential role, ADC circuits have been well studied over 40 years, and many problems associated with them have already been solved. However in recent years, a new species of ADCs has appeared, and since then attracted lots of attention. These are ultra-high-speed (often greater than 40GS/s) time-interleaved ADCs of low or medium resolution (around 6 to 8 bit) built in CMOS processes. Although such ADCs can be used in high-speed electronic measurement equipment and radar systems, the recent driving force behind them is next generation 100Gbps/400Gbps fiber optical transceivers. These transceivers take advantage of ultra-high-speed ADCs and digital-signal-processors (DSPs) to enable ultra-high data-rate communications in long-haul networks (city-to-city, transcontinental, and transoceanic fiber links), metro networks (fibers that connect enterprises in metropolitan areas), and data centers (fiber links within data center infrastructures). At such high sampling rate, massively time-interleaved successive-approximation ADC (SAR ADC) architecture has emerged as the dominant solution due to its excellent power efficiency. Several recent works has demonstrated success in achieving high sampling rate. However, the sampling network has become the bottleneck that limits the input bandwidth in these ADCs. It is apparent that conventional switch-based track-and-hold (T&H) circuit cannot satisfy the >20GHz bandwidth requirement. In addition, it is unclear what the optimal interleaving configuration is. Each state-of-the-art design adopts a different interleaving configuration - from straightforward conventional 1-rank interleaving to 2-rank hierarchical sampling or even 3 ranks. How to partition interleaving factors among different ranks has not yet been investigated. Furthermore, asynchronous SAR sub-ADCs are often used in these designs to push the sampling rate even further. The well-known sparkle-code issues caused by comparator meta-stability in asynchronous SARs can significantly increase the Bit-Error-Rate (BER) of the transceivers unless power hungry error correction coding are implemented in the system. Although many works in the literature attempted to deal with the meta-stability in asynchronous SARs, the effectiveness of these approaches have not been fully demonstrated. In this thesis, I will first propose a new cascode-based T&H circuits to improve the ADC bandwidth beyond the limit of conventional switch-based T&H circuits. Then, a system design and optimization methodology of hierarchical time-interleaved sampling network is presented in the context of cascode T&H. To deal with sparkle-code issue in asynchronous SAR sub-ADCs, a new back-end meta-stability correction technique is employed. An extensive statistical analysis is provided to verify the correction algorithm can greatly reduce sparkle-code error-rates. To further demonstrate the effectiveness of the proposed circuits and techniques, two prototype ADCs have been implemented. The first 7b 12.5GS/s hierarchically time-interleaved ADC in 65nm CMOS process demonstrates 29.4dB SNDR and >25GHz bandwidth. The later 6b 46GS/s ADC in 28nm CMOS employs asynchronous SAR sub-ADC design with back-end meta-stability correction. The measurement results show it achieves sparkle-code error free operation over 1e10 samples in addition to achieving >23GHz bandwidth and 25.2dB SNDR. The power consumption is 381mW from 1.05V/1.6V supplies, and the FOM is 0.56pJ/conversion-step.
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