Author : Sara Karimi
Publisher :
ISBN 13 :
Total Pages : 135 pages
Book Rating : 4.:/5 (113 download)
Book Synopsis Prediction Modeling for Design Space Exploration in Optical Network on Chip by : Sara Karimi
Download or read book Prediction Modeling for Design Space Exploration in Optical Network on Chip written by Sara Karimi and published by . This book was released on 2017 with total page 135 pages. Available in PDF, EPUB and Kindle. Book excerpt: In at least a decade chip multiprocessors (CMP) have been dominating new commercialreleases due to computational advantages of parallel computing cores on a single chip. Networkon Chip (NoC) has emerged as an interconnection network of CMPs. But significant bandwidththat is required for multicore chips is becoming a bottleneck in the traditional (electrical)network on chip, due to delays caused by long wires in the electric NoC. Integration of photoniclinks with traditional electronic interconnects proposes a promising solution for this challenge.Since there are numerous design parameters for opto-electrical network architectures, an accurateevaluation is needed to study the impact of each design parameter on network performance, andto provide the most suitable network for a given set of applications, a power or a performancegoal. In this thesis, we present a prediction modeling technique for design space exploration ofan opto-electrical network on chip. Our proposed model accurately predicts delay (includesnetwork packet latency and network contention delay) and energy (includes static and dynamicenergy consumption) of the network. Specifically, this work addresses the fundamental challengeof accurate estimation of desired metrics without having to incur high simulation cost ofnumerous configurations of the optical network on chip architecture. We reduce the number ofrequired simulations by accurately selecting the parameters that have the most impact on thenetwork. Furthermore, we sparsely and randomly sample the designs build using theseparameters from an Optical Network on Chip (ONoC) design space, and simulate only thesampled designs. We validate our model with three different applications executing on a large setof network configurations in a large optical network on chip design space. We achieve averageerror rates (root relative squared error) as low as 5.5% for the delay and 3.05% for the energyconsumption.
