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Compiler Analysis For Cache Coherence
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Book Synopsis Compiler Analysis for Cache Coherence by : Lynn Choi
Download or read book Compiler Analysis for Cache Coherence written by Lynn Choi and published by . This book was released on 1996 with total page 44 pages. Available in PDF, EPUB and Kindle. Book excerpt: Abstract: "In this paper, we present compiler algorithms for detecting references to stale data in shared-memory multiprocessors. The algorithm consists of two key analysis techniques, stale reference detection and locality preserving analysis. While the stale reference detection finds the memory reference patterns that may violate cache coherence, the locality preserving analysis minimizes the number of such stale references by analyzing both temporal and spatial reuses. By computing the regions referenced by arrays inside loops, we extend the previous scalar algorithms [8] for more precise analysis. We develop a full interprocedural array data-flow algorithm, which performs both bottom- up side-effect analysis and top-down context analysis on the procedure call graph to further exploit locality across procedure boundaries. The interprocedural algorithm eliminates cache invalidations at procedure boundaries, which were assumed in the previous compiler algorithms [9]. We have fully implemented the algorithm in the Polaris parallelizing compiler [27]. Using execution-driven simulations on Perfect Club benchmarks, we demonstrate how unnecessary cache misses can be eliminated by the automatic stale reference detection. The algorithm can be used to implement cache coherence in the shared-memory multiprocessors that do not have hardware directories, such as Cray T3D [20]."
Book Synopsis Hardware and Compiler-directed Cache Coherence in Large-scale Multiprocessors by : Lynn Choi
Download or read book Hardware and Compiler-directed Cache Coherence in Large-scale Multiprocessors written by Lynn Choi and published by . This book was released on 1996 with total page 40 pages. Available in PDF, EPUB and Kindle. Book excerpt: Abstract: "In this paper, we study a hardware-supported, compiler-directed (HSCD) cache coherence scheme, which can be implemented on a large-scale multiprocessor using off-the-shelf microprocessors, such as the Cray T3D. The scheme can be adapted to various cache organizations, including multi-word cache lines and byte-addressable architectures. Several system related issues, including critical sections, inter-thread communication, and task migration have also been addressed. The cost of the required hardware support is minimal and proportional to the cache size. The necessary compiler algorithms, including intra- and interprocedural array data flow analysis, have been implemented on the Polaris parallelizing compiler [33]. From our simulation study using the Perfect Club benchmarks [5], we found that in spite of the conservative analysis made by the compiler, the performance of the proposed HSCD scheme can be comparable to that of a full-map hardware directory scheme. Given its comparable performance and reduced hardware cost, the proposed scheme can be a viable alternative for large-scale multiprocessors such as the Cray T3D, which rely on users to maintain data coherence."
Book Synopsis Hardware and Compiler Support for Cache Coherence in Large-scale Shared-memory Multiprocessors by : Lynn Choi
Download or read book Hardware and Compiler Support for Cache Coherence in Large-scale Shared-memory Multiprocessors written by Lynn Choi and published by . This book was released on 1996 with total page 300 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis Languages and Compilers for Parallel Computing by : Chua-Huang Huang
Download or read book Languages and Compilers for Parallel Computing written by Chua-Huang Huang and published by Springer Science & Business Media. This book was released on 1996-01-24 with total page 618 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book presents the refereed proceedings of the Eighth Annual Workshop on Languages and Compilers for Parallel Computing, held in Columbus, Ohio in August 1995. The 38 full revised papers presented were carefully selected for inclusion in the proceedings and reflect the state of the art of research and advanced applications in parallel languages, restructuring compilers, and runtime systems. The papers are organized in sections on fine-grain parallelism, interprocedural analysis, program analysis, Fortran 90 and HPF, loop parallelization for HPF compilers, tools and libraries, loop-level optimization, automatic data distribution, compiler models, irregular computation, object-oriented and functional parallelism.
Book Synopsis Interprocedural Compiler Analysis for Reducing Memory Latency by : Trung Ngoc Nguyen
Download or read book Interprocedural Compiler Analysis for Reducing Memory Latency written by Trung Ngoc Nguyen and published by . This book was released on 1996 with total page 406 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis Visible Synchronization Based Cache Coherence by : Krishna Kumar
Download or read book Visible Synchronization Based Cache Coherence written by Krishna Kumar and published by . This book was released on 1997 with total page 0 pages. Available in PDF, EPUB and Kindle. Book excerpt: In large scale machines, thousands of processor cycles, in other words, missed opportunities to issue floating point instructions, may be lost while waiting for a high latency synchronization or memory operation to complete, or a stall in an instruction pipeline to be dealt with. Latency is avoided by bringing data to a nearby locale for future reference (e.g., caching) while latency is tolerated by overlapping data movement with something useful. The issue of cache coherence arises whenever there are multiple copies of a shared datum in different caches of a shared-memory multiprocessor system. It is in order to maintain consistency between these multiple copies that cache coherence protocols are employed. The efficiency of latency avoidance methods is largely dependent upon the minimization of coherence traffic in the coherence protocol used to maintain cache coherency. Cache coherence protocols in general can be divided into two classes: hardware implemented ones and compiler implemented ones. Hardware implemented ones lead to large coherence traffic, and large state storage space. Conventional compiler implemented ones involve indiscriminate wasteful invalidation. There is also redundancy between synchronization operations and coherence operations. We seek to eliminate both weaknesses, by letting visible synchronization directly coordinate changes in the writability of shared data. We propose to add scalable compiler managed caches to a TERA-like multithreaded multiprocessor architecture, with user/compiler knowledge (i.e., alias analysis, dependence analysis and user directives) used to eliminate essentially all coherence traffic. To preserve scalability, we aim to use latency tolerance methods like switch-on-every-cycle multithreading, and augment this with simple, low-latency cache coherence protocols such as our visible synchronization based one.
Book Synopsis Languages and Compilers for Parallel Computing by : Sanjay Rajopadhye
Download or read book Languages and Compilers for Parallel Computing written by Sanjay Rajopadhye and published by Springer. This book was released on 2013-01-18 with total page 307 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book constitutes the thoroughly refereed post-conference proceedings of the 24th International Workshop on Languages and Compilers for Parallel Computing, LCPC 2011, held in Fort Collins, CO, USA, in September 2011. The 19 revised full papers presented and 19 poster papers were carefully reviewed and selected from 52 submissions. The scope of the workshop spans the theoretical and practical aspects of parallel and high-performance computing, and targets parallel platforms including concurrent, multithreaded, multicore, accelerator, multiprocessor, and cluster systems.
Book Synopsis Languages and Compilers for Parallel Computing by : Keith Cooper
Download or read book Languages and Compilers for Parallel Computing written by Keith Cooper and published by Springer Science & Business Media. This book was released on 2011-03-07 with total page 286 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book constitutes the thoroughly refereed post-proceedings of the 23rd International Workshop on Languages and Compilers for Parallel Computing, LCPC 2010, held in Houston, TX, USA, in October 2010. The 18 revised full papers presented were carefully reviewed and selected from 47 submissions. The scope of the workshop spans foundational results and practical experience, and targets all classes of parallel platforms in- cluding concurrent, multithreaded, multicore, accelerated, multiprocessor, and cluster systems.
Book Synopsis Hardware and Compiler-directed Cache Coherence in Large-scale Multiprocessors: Design Considerations and Preformance Study by : L. Choi
Download or read book Hardware and Compiler-directed Cache Coherence in Large-scale Multiprocessors: Design Considerations and Preformance Study written by L. Choi and published by . This book was released on 1996 with total page 37 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis Compiler Optimizations for Cache Locality and Coherence by : University of Rochester. Dept. of Computer Science
Download or read book Compiler Optimizations for Cache Locality and Coherence written by University of Rochester. Dept. of Computer Science and published by . This book was released on 1994 with total page 29 pages. Available in PDF, EPUB and Kindle. Book excerpt: Abstract: "Almost every modern processor is designed with a memory hierarchy organized into several levels, each of which is smaller, faster, and more expensive than the level below. High performance requires the effective use of the cached data, i.e. cache locality. Smart compiler transformations can relieve the programmer from hand-optimizing for the specific machine architectures. In a multiprocessor system, data inconsistency may occur between memory and caches. For example, the memory and multiple caches may have inconsistent copies of the same cache block. This introduces the problem of cache coherence. Several cache coherence protocols have been developed to maintain data coherence for multiple processors. Since multiple variables are located in the same block, it may cause the problem of false sharing, which has been identified by many researchers as a major obstacle to high performance. Therefore, in a multiprocessor system, we need to avoid false sharing as well as exploit cache locality. In this paper, we first develop a new data reuse model and an algorithm called height reduction to improve cache locality. The advantage of this algorithm is that it can improve band matrix programs as well as dense matrix programs. It is more accurate and general than the existing techniques on improving cache locality, which were developed to optimize dense matrix programs. Then with the height reduction algorithm, we extend loop tiling to exploit not only intra-tile data locality but also inter-tile data locality. We call the new tiling affinity tiling. Our experiments show that affinity tiling is less sensitive to the choice of the tile size. Finally, we show that the algorithm also helps to eliminate or reduce false sharing in multiprocessor systems. With the height reduction algorithm and affinity tiling, significant performance improvement (speedups from 2.5 to 10) has been ovserved on HP workstations and KSR1 multiprocessors."
Book Synopsis A Primer on Memory Consistency and Cache Coherence by : Daniel Sorin
Download or read book A Primer on Memory Consistency and Cache Coherence written by Daniel Sorin and published by Morgan & Claypool Publishers. This book was released on 2011-03-02 with total page 214 pages. Available in PDF, EPUB and Kindle. Book excerpt: Many modern computer systems and most multicore chips (chip multiprocessors) support shared memory in hardware. In a shared memory system, each of the processor cores may read and write to a single shared address space. For a shared memory machine, the memory consistency model defines the architecturally visible behavior of its memory system. Consistency definitions provide rules about loads and stores (or memory reads and writes) and how they act upon memory. As part of supporting a memory consistency model, many machines also provide cache coherence protocols that ensure that multiple cached copies of data are kept up-to-date. The goal of this primer is to provide readers with a basic understanding of consistency and coherence. This understanding includes both the issues that must be solved as well as a variety of solutions. We present both highlevel concepts as well as specific, concrete examples from real-world systems. Table of Contents: Preface / Introduction to Consistency and Coherence / Coherence Basics / Memory Consistency Motivation and Sequential Consistency / Total Store Order and the x86 Memory Model / Relaxed Memory Consistency / Coherence Protocols / Snooping Coherence Protocols / Directory Coherence Protocols / Advanced Topics in Coherence / Author Biographies
Book Synopsis Languages and Compilers for Parallel Computing by : Siddharta Chatterjee
Download or read book Languages and Compilers for Parallel Computing written by Siddharta Chatterjee and published by Springer. This book was released on 2003-06-26 with total page 395 pages. Available in PDF, EPUB and Kindle. Book excerpt: LCPC’98 Steering and Program Committes for their time and energy in - viewing the submitted papers. Finally, and most importantly, we thank all the authors and participants of the workshop. It is their signi cant research work and their enthusiastic discussions throughout the workshopthat made LCPC’98 a success. May 1999 Siddhartha Chatterjee Program Chair Preface The year 1998 marked the eleventh anniversary of the annual Workshop on Languages and Compilers for Parallel Computing (LCPC), an international - rum for leading research groups to present their current research activities and latest results. The LCPC community is interested in a broad range of te- nologies, with a common goal of developing software systems that enable real applications. Amongthetopicsofinteresttotheworkshoparelanguagefeatures, communication code generation and optimization, communication libraries, d- tributed shared memory libraries, distributed object systems, resource m- agement systems, integration of compiler and runtime systems, irregular and dynamic applications, performance evaluation, and debuggers. LCPC’98 was hosted by the University of North Carolina at Chapel Hill (UNC-CH) on 7 - 9 August 1998, at the William and Ida Friday Center on the UNC-CH campus. Fifty people from the United States, Europe, and Asia attended the workshop. The program committee of LCPC’98, with the help of external reviewers, evaluated the submitted papers. Twenty-four papers were selected for formal presentation at the workshop. Each session was followed by an open panel d- cussion centered on the main topic of the particular session.
Book Synopsis The Cache Coherence Problem in Shared-Memory Multiprocessors by : Igor Tartalja
Download or read book The Cache Coherence Problem in Shared-Memory Multiprocessors written by Igor Tartalja and published by Wiley-IEEE Computer Society Press. This book was released on 1996-02-13 with total page 368 pages. Available in PDF, EPUB and Kindle. Book excerpt: The book illustrates state-of-the-art software solutions for cache coherence maintenance in shared-memory multiprocessors. It begins with a brief overview of the cache coherence problem and introduces software solutions to the problem. The text defines and details static and dynamic software schemes, techniques for modeling performance evaluation mechanisms, and performance evaluation studies.
Book Synopsis Euro-Par 2000 Parallel Processing by : Arndt Bode
Download or read book Euro-Par 2000 Parallel Processing written by Arndt Bode and published by Springer. This book was released on 2003-06-26 with total page 1395 pages. Available in PDF, EPUB and Kindle. Book excerpt: Euro-Par – the European Conference on Parallel Computing – is an international conference series dedicated to the promotion and advancement of all aspects of parallel computing. The major themes can be divided into the broad categories of hardware, software, algorithms, and applications for parallel computing. The objective of Euro-Par is to provide a forum within which to promote the dev- opment of parallel computing both as an industrial technique and an academic discipline, extending the frontier of both the state of the art and the state of the practice. This is particularlyimportant at a time when parallel computing is - dergoing strong and sustained development and experiencing real industrial take up. The main audience for and participants of Euro-Par are seen as researchers in academic departments, government laboratories, and industrial organisations. Euro-Par’s objective is to become the primarychoice of such professionals for the presentation of new results in their speci?c areas. Euro-Par is also interested in applications that demonstrate the e?ectiveness of the main Euro-Par themes. Euro-Par now has its own Internet domain with a permanent Web site where the historyof the conference series is described: http://www. euro-par. org. The Euro-Par conference series is sponsored bythe Association of Computer Machineryand the International Federation of Information Processing.
Book Synopsis Architecture and Compiler Support for Parallel Consistency, Coherence, and Security by : Rui Zhang (Ph. D. in computer science)
Download or read book Architecture and Compiler Support for Parallel Consistency, Coherence, and Security written by Rui Zhang (Ph. D. in computer science) and published by . This book was released on 2020 with total page 147 pages. Available in PDF, EPUB and Kindle. Book excerpt: The widespread use of multicore processors has made parallelism a necessity for performance. However, parallelism allows programs to share physical computing resources, such as memory and processor caches, which presents challenges for computer systems to ensure correct and secure parallel executions. Specifically, these challenges include: 1) providing strong memory consistency to programs with data races while allowing best-effort progress; 2) providing data-race-free (DRF) programs with simple, efficient cache coherence; and 3) ensuring information security for programs that run in parallel. These challenges in parallel consistency, coherence, and security motivate this work. The thesis of our work is that parallel systems can get the benefits of strong consistency, simple and efficient coherence, and strong security guarantees with little performance degradation or human effort. The goal in this dissertation is to make contributions by presenting and proposing architecture and compiler support to ensure correct and secure parallelism with minimal extra costs. Modern memory models make the DRF assumption and provide strong, well-defined end-to-end memory consistency only for DRF programs. Prior work has proposed fail-stop memory consistency to provide well-defined behaviors for all programs. However, fail-stop consistency can lead to unexpected failures in the presence of data races, imperiling performance or progress. To help systems get the benefits of fail-stop memory consistency while minimizing the costs of failures, this dissertation presents a set of architectural mechanisms that provide best-effort avoidance of failures on top of systems that provide fail-stop consistency. Unlike memory consistency models, mainstream cache coherence protocols such as MESI are designed to enforce coherence for both DRF and non-DRF programs and thus are complex. Specifically, MESI requires numerous transient states, a shared directory, and support for core-to-core communication. As DRF is widely assumed by today’s language-level memory models, this dissertation explores the possibility of providing simpler cache coherence protocols under the DRF assumption and presents a simple, efficient self-invalidation-based coherence protocol that eliminates MESI’s expensive requirements. The key insights in this work lie in its novel design that has no shared ownership metadata and that uses lightweight mechanisms to avoid many unnecessary self-invalidations. The fact that programs share physical computing resources such as memory and processor caches presents not only correctness challenges but also security threats. Among such threats, particularly worrisome are cache side-channel attacks, which have been demonstrated to be potent enough to facilitate the deduction of sensitive information in realistic scenarios. To protect programs from cache side-channel attacks, we propose automatic compiler support for strong, efficient cache side-channel protection based on widely available commodity hardware transactional memory (HTM). This work consists of a set of program analysis and instrumentation techniques that detect and analyze sensitive data and code, delimit transactions, and insert code to protect sensitive data and code. By making contributions in parallel consistency, coherence, and security, this dissertation aims to address challenges that parallelism faces to ensure correct and secure executions. Our proposed architecture support for best-effort avoidance of failures provides strong consistency without the costs of consistency failures. Our proposed coherence protocol extends the design limit of cache coherence on complexity under the DRF assumption. Last but not least, our proposed techniques of automatic cache side-channel protection help developers get the benefit of secure parallelism with little human effort. Overall, this dissertation significantly advances the state of the art in parallel consistency, coherence, and security.
Book Synopsis High Performance Compilers for Parallel Computing by : Michael Joseph Wolfe
Download or read book High Performance Compilers for Parallel Computing written by Michael Joseph Wolfe and published by Addison Wesley. This book was released on 1996 with total page 600 pages. Available in PDF, EPUB and Kindle. Book excerpt: Software -- Operating Systems.
Book Synopsis Languages and Compilers for Parallel Computing by : Lawrence Rauchwerger
Download or read book Languages and Compilers for Parallel Computing written by Lawrence Rauchwerger and published by Springer Nature. This book was released on 2019-11-19 with total page 313 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book constitutes the proceedings of the 30th International Workshop on Languages and Compilers for Parallel Computing, LCPC 2017, held in College Station, TX, USA, in October 2017. The 17 full papers presented together with abstracts of 5 keynote talks, 11 invited speakers and 4 poster papers in this volume were carefully reviewed and selected from 26 submissions. LCPC encourages submissions that go outside its original scope of scientific computing to diverse areas that are enable or enhanced by the power of parallel systems such as mobile computing, big data, relevant aspects of machine learning, data centers, cognitive computing, etc. LCPC strongly encourages personal interaction and technical discussions along the initial material.
