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The Reduction And Cancellation Of Phase Noise In Digital Frequency Synthesizers And Quadrature Receivers
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Book Synopsis The Reduction and Cancellation of Phase Noise in Digital Frequency Synthesizers and Quadrature Receivers by : Zuow-Zun Chen
Download or read book The Reduction and Cancellation of Phase Noise in Digital Frequency Synthesizers and Quadrature Receivers written by Zuow-Zun Chen and published by . This book was released on 2016 with total page 100 pages. Available in PDF, EPUB and Kindle. Book excerpt: Circuit and system techniques for reducing phase noise in frequency synthesizers, and cancelling phase noise effect in quadrature receivers are presented. Phase noise performance of digital phase-locked loops (PLLs) is limited by the time resolution of time-to-digital converters (TDC). In contrast to TDCs in the past that concentrate on the arrival time difference between the divider feedback edge and the reference signal edge. Our approach extracts the timing information that is embedded in voltage domain. This approach not only achieves a higher time resolution, lower phase noise, but also consumes less power. A digital background calibration circuit is also presented to reduce the output spurious tones when the digital PLL operates under fractional-N divisions. Ring Oscillators (ROs) have the advantage of small area, wide tuning range, and multiphase output. However, their higher phase noise and higher sensitivity to supply noise may seriously deteriorate the wanted signal in wireless receivers. To circumvent this non-ideality, a low overhead phase noise cancellation technique for ring oscillator-based quadrature receivers is presented. The proposed technique operates in background and extracts ring oscillator phase noise as well as supply-induced phase noise from the digital PLL. The obtained phase noise information is then used to restore the randomly rotated baseband signal in digital domain. In recent years, the unsilenced band at 57~64 GHz frequency range has motivated the building of high-data rate radio systems targeting wireless personal area network (WPAN) applications. To address this demand, a low-noise wide-band integer-N PLL is presented which serves as the carrier generator of a 60 GHz heterogeneous transceiver. The PLL employs sub-sampling phase detection technique to achieve low-noise performance, and provides 48 GHz LO and 12 GHz IF carrier signals for the heterogeneous transceiver.
Book Synopsis Reducing Phase Noise and Spurious Tones in Fractional-n Synthesizers by :
Download or read book Reducing Phase Noise and Spurious Tones in Fractional-n Synthesizers written by and published by . This book was released on 2009 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: A frequency synthesizer is a control system which employs a reference signal from a component, such as a crystal oscillator, with excellent phase and frequency stability to synthesize higher frequencies with similarly desirable characteristics. Such a control system is at the heart of many communication schemes. Due to the digital circuitry used in frequency synthesis, it is relatively straightforward to synthesize frequencies at integer multiples of the reference signal frequency. A synthesizer which achieves this is called an integer-N frequency synthesizer. The main challenge in the design of integer-N synthesizers is to reduce phase noise introduced by circuitry while achieving a needed frequency resolution. Noise can be spectrally spread by conversions in the loop which are non-linear, so the strategy to reduce noise is two-fold. Control-loop and circuit design techniques can be used to reduce device noise, but it is also important to make sure that the noise performance is not degraded by spectral spreading within the loop. This thesis addresses primarily the latter approach with the design and implementation of circuits targeting a specific conversion within the loop. Frequency resolution of a synthesizer can be improved by introducing additional circuitry and complexity. This additional complexity makes it possible to multiply the reference frequency by a fractional number and thus achieve higher frequency resolution. A control system which achieves this is called a fractional-N frequency synthesizer. The cost associated with the increased frequency resolution is a form of noise that is deterministic called spurious noise. This spurious noise can also be spread and amplified by non-linear conversions in the control loop. A quantitative understanding of the magnitude of this noise that is not readily available in the literature was developed in this research. A comparison between several implementations of integrated frequency synthesis was also carried out in this research with the intent of providing guidelines to produce a better performing synthesizer. These implementations differ in key components of the loop where linearity is of particular importance.
Book Synopsis Multi-GHz Frequency Synthesis & Division by : Hamid R. Rategh
Download or read book Multi-GHz Frequency Synthesis & Division written by Hamid R. Rategh and published by Springer Science & Business Media. This book was released on 2001-10-31 with total page 157 pages. Available in PDF, EPUB and Kindle. Book excerpt: Demand for wireless local area network systems has led to new frequency bands and new standards to accommodate higher data rates. Moreover, opportunities are increasing for the development of low- cost integrated WLAN systems. This guide for RF and high-speed analog circuit designers and students as well as wireless engineers studies the phase-locked loop as a basic building block of frequency synthesizers and WLAN receivers. It provides guidelines and engineering solutions for the design of loop filters in high- frequency PLLs. Rategh (Tavanza Inc.) and Lee (Stanford U.) discuss the different analog and digital frequency division techniques and introduce injection-locked frequency dividers as an alternative to conventional frequency dividers. c. Book News Inc.
Book Synopsis Enabling Techniques for Low Power, High Performance Fractional-N Frequency Synthesizers by : Ashok Swaminathan
Download or read book Enabling Techniques for Low Power, High Performance Fractional-N Frequency Synthesizers written by Ashok Swaminathan and published by . This book was released on 2006 with total page 84 pages. Available in PDF, EPUB and Kindle. Book excerpt: Delta-sigma fractional-N phase-locked loops are used to generate high quality radio-frequency signals for use in wireless applications. To reduce the phase noise inherent to these systems, a digital-to-analog converter is used to cancel the error introduced by the fractional division process, however matching between the digital-to-analog converter and the phase-locked loop circuitry place a limit on the amount of phase noise reduction that can be achieved. Furthermore, circuit non-linearity results in the appearance of spurious tones in the phase-locked loop output. This dissertation outlines a calibration technique, and a digital quantization technique that provide solutions to these two problems. The calibration technique results in improved phase noise performance by adjusting the digital-to-analog converter gain, and thus providing better matching between the phase-locked loop circuitry and digital-to-analog converter. The digital quantization technique results in no spurious tones when specified non-linearity is applied to the quantizer output sequence and error. The calibration technique was implemented in an integrated circuit, which achieves state-of-the-art performance when compared to currently published phase-locked loops and allows for all circuitry to be integrated onto a single chip. Chapter 1 presents the calibration technique, as well as a theoretical analysis of the stability. Chapter 2 presents details on the digital quantization technique, and a mathematical proof of the absence of spurious tones. In chapter 3, results from an implemented circuit are presented, which verify the behaviour of the technique presented in chapter 1.
Book Synopsis Technique of In-band Phase Noise Reduction in Fractional-N Frequency Synthesizers by : 王俊彬
Download or read book Technique of In-band Phase Noise Reduction in Fractional-N Frequency Synthesizers written by 王俊彬 and published by . This book was released on 2016 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis An Adaptive Phase Quantization Noise Cancellation Architecture for [delta Sigma] Fractional-N Frequency Synthesizers by : Jonathon Christopher Stiff
Download or read book An Adaptive Phase Quantization Noise Cancellation Architecture for [delta Sigma] Fractional-N Frequency Synthesizers written by Jonathon Christopher Stiff and published by . This book was released on 2015 with total page 90 pages. Available in PDF, EPUB and Kindle. Book excerpt: A fractional-N PLL phase quantization cancellation architecture using adaptive digital delay word scaling is presented and demonstrated. A digital sign-error adaptive filter utilizing the 1-bit quantized PLL phase error and the feedback divider delta-sigma modulator accumulated error generates the optimal control word scaling for a phase cancelling digital delay. A comprehensive analytic phase noise model is derived and compared to time-domain simulation and measurement. The proposed fractional-N synthesizer, with a 2.4 GHz center frequency VCO is fabricated on a PCB with commercially available integrated circuits as a proof of concept. The synthesizer output frequency range is 144-156 MHz with 2 ppm resolution for a 20 MHz crystal oscillator reference. The adaptive phase cancellation is measured to reduce phase noise by as much as 25 dB.
Book Synopsis A Jitter-cleaning Fractional-N Frequency Synthesizer with 10 Hz-40 KHz Digitally Programmable Loop Bandwidth by : Chih-Wei Yao
Download or read book A Jitter-cleaning Fractional-N Frequency Synthesizer with 10 Hz-40 KHz Digitally Programmable Loop Bandwidth written by Chih-Wei Yao and published by . This book was released on 2012 with total page 101 pages. Available in PDF, EPUB and Kindle. Book excerpt: This dissertation contains three parts. In the first part, the analysis and circuits of a jittercleaning fractional-N frequency synthesizer is presented. In the second part, a low phase noise and low I/Q mismatch quadrature VCO is presented. In the third part, a low phase noise digital PLL is presented. For the first part, the design utilizes a dual-loop architecture, which is suitable for integration in an SoC environment. The primary loop is a digital PLL with a second-order noise shaping phase-error ADC. The secondary loop is a fractional-N PLL implementing the digitally controlled oscillator inside the primary loop, and it locks to an external clean reference clock to reduce the phase noise and to improve the frequency stability of the on-chip oscillator. For the second part, a tail-tank coupling technique that combines two complementary differential LC-VCOs to form a quadrature LC-VCO is presented. This technique reduces phase noise by providing additional energy storages for noise redistribution and by canceling out most of the noise injected by transistors when they operate in the triode region. The resulting noise factor is close to the theoretical minimum value. For the third part, a 2.8 to 3.2 GHz fractional-N digital PLL is presented. A divider with two-stage retiming improves linearity to reduce fractional spurs without increasing the in-band noise floor. An ADC is employed to boost TDC resolution by five times to achieve 2 ps effective resolution. A dither-less DCO with an inductively coupled fine-tune varactor bank improves tuning step-size to 20 kHz. With a 52 MHz reference clock and a loop-bandwidth of 950 kHz, this prototype achieves 230 fs rms jitter integrated from 1 kHz to 40 MHz offset while drawing 17 mW from a 1.8V supply. A FOM of -240.4 dB is achieved.
Book Synopsis Digital Radio System Design by : Grigorios Kalivas
Download or read book Digital Radio System Design written by Grigorios Kalivas and published by John Wiley & Sons. This book was released on 2009-10-23 with total page 472 pages. Available in PDF, EPUB and Kindle. Book excerpt: A systematic explanation of the principles of radio systems, Digital Radio System Design offers a balanced treatment of both digital transceiver modems and RF front-end subsystems and circuits. It provides an in-depth examination of the complete transceiver chain which helps to connect the two topics in a unified system concept. Although the book tackles such diverse fields it treats them in sufficient depth to give the designer a solid foundation and an implementation perspective. Covering the key concepts and factors that characterise and impact radio transmission and reception, the book presents topics such as receiver design, noise and distortion. Information is provided about more advanced aspects of system design such as implementation losses due to non-idealities. Providing vivid examples, illustrations and detailed case-studies, this book is an ideal introduction to digital radio systems design. Offers a balanced treatment of digital modem and RF front-end design concepts for complete transceivers Presents a diverse range of topics related to digital radio design including advanced transmission and synchronization techniques with emphasis on implementation Provides guidance on imperfections and non-idealities in radio system design Includes detailed design case-studies incorporating measurement and simulation results to illustrate the theory in practice
Book Synopsis Digital Frequency Synthesis Demystified by : Bar-Giora Goldberg
Download or read book Digital Frequency Synthesis Demystified written by Bar-Giora Goldberg and published by Elsevier. This book was released on 2000-02-20 with total page 354 pages. Available in PDF, EPUB and Kindle. Book excerpt: · In-depth coverage of modern digital implementations of frequency synthesis architectures· Numerous design examples drawn from actual engineering projectsDigital frequency synthesis is used in modern wireless and communications technologies such as radar, cellular telephony, satellite communications, electronic imaging, and spectroscopy. This is book is a comprehensive overview of digital frequency synthesis theory and applications, with a particular emphasis on the latest approaches using fractional-N phase-locked loop technology. In-depth coverage of modern digital implementations of frequency synthesis architectures Numerous design examples drawn from actual engineering projects
Author :Shaojun Wu Publisher :Library and Archives Canada = Bibliothèque et Archives Canada ISBN 13 :9780494019887 Total Pages :182 pages Book Rating :4.0/5 (198 download)
Book Synopsis A Low Phase Noise Fast-settling PLL Frequency Synthesizer for CDMA Receivers [microform] by : Shaojun Wu
Download or read book A Low Phase Noise Fast-settling PLL Frequency Synthesizer for CDMA Receivers [microform] written by Shaojun Wu and published by Library and Archives Canada = Bibliothèque et Archives Canada. This book was released on 2004 with total page 182 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis Research on Reducing Out-of-band Phase Noise of Fractional-n Frequency Synthesizer by : 林嘉豪
Download or read book Research on Reducing Out-of-band Phase Noise of Fractional-n Frequency Synthesizer written by 林嘉豪 and published by . This book was released on 2014 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis Architectures for RF Frequency Synthesizers by : Cicero S. Vaucher
Download or read book Architectures for RF Frequency Synthesizers written by Cicero S. Vaucher and published by Springer Science & Business Media. This book was released on 2006-04-18 with total page 268 pages. Available in PDF, EPUB and Kindle. Book excerpt: This text describes a conceptual framework for analyzing the performance of PLL frequency synthesizers, and presents optimization procedures for the different performance aspects. It contains basic information and in-depth knowledge, widely illustrated with practical design examples used in industrial products.
Book Synopsis Mitigation of Random and Deterministic Noise in Mixed Signal Systems with Examples in Frequency Synthesizer Systems by : Thomas Weston Burress
Download or read book Mitigation of Random and Deterministic Noise in Mixed Signal Systems with Examples in Frequency Synthesizer Systems written by Thomas Weston Burress and published by . This book was released on 2011 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: RF frequency synthesizer systems are prevalent in today's electronics. In a synthesizer there is a sensitive analog oscillator that may be affected by two different types of noise. The first is random noise injection from active devices. This results in phase noise in the synthesizer's spectrum. The second noise source is deterministic. A digital frequency divider with high-amplitude switching is an example of such a deterministic source. This noise enters the system through various forms of electric or magnetic field coupling and manifests itself as spurs or pulling. Both forms of noise can adversely affect system performance. We will first summarize methods for reducing noise. These already known steps have to do with layout techniques, device geometry, and general synthesizer topologies. Then we will show ways to isolate noisy interfering circuits from the sensitive analog systems. Finally, we present some considerations for reducing the effects of random noise. A power supply filter can improve the effects of deterministic noise such as undesired signals on the supply line. We show several ways to improve the rejection of high frequency supply noise (characterized by the power supply rejection ratio or PSRR) through the design of a voltage regulator. The emphasis is on new techniques for obtaining good PSRR at S-band frequencies and above. To validate the techniques, we designed a regulator in Peregrine Semiconductor's .25[mu]m ULTRA CMOS Silicon on Sapphire process. It produces a 2.5V output with an input ranging from 2.6V to 5V and has a maximum current sourcing of 70mA. The regulator's low drop out performance is 60mV with no load and it achieves a power supply ripple reduction of 29.8 dB at 500 MHz. To address random noise in synthesizers, the thesis provides preliminary investigation of an oscillator topology change that has been proposed in the literature. This proposed change reduces the phase noise of the oscillator within the overall system. A differential cross-coupled design is the usual topology of choice, but it is not optimal for noise performance. We investigate current noise injection in the traditional design and present an updated design that uses a differential Colpitts oscillator as an alternative to classic cross-coupled designs.
Book Synopsis Phase noise in signal sources : [theorie and applications] by : W. P. Robins
Download or read book Phase noise in signal sources : [theorie and applications] written by W. P. Robins and published by . This book was released on 1982 with total page 336 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis Design of High-speed Communication Circuits by : Ramesh Harjani
Download or read book Design of High-speed Communication Circuits written by Ramesh Harjani and published by World Scientific. This book was released on 2006 with total page 233 pages. Available in PDF, EPUB and Kindle. Book excerpt: MOS technology has rapidly become the de facto standard for mixed-signal integrated circuit design due to the high levels of integration possible as device geometries shrink to nanometer scales. The reduction in feature size means that the number of transistor and clock speeds have increased significantly. In fact, current day microprocessors contain hundreds of millions of transistors operating at multiple gigahertz. Furthermore, this reduction in feature size also has a significant impact on mixed-signal circuits. Due to the higher levels of integration, the majority of ASICs possesses some analog components. It has now become nearly mandatory to integrate both analog and digital circuits on the same substrate due to cost and power constraints. This book presents some of the newer problems and opportunities offered by the small device geometries and the high levels of integration that is now possible. The aim of this book is to summarize some of the most critical aspects of high-speed analog/RF communications circuits. Attention is focused on the impact of scaling, substrate noise, data converters, RF and wireless communication circuits and wireline communication circuits, including high-speed I/O. Contents: Achieving Analog Accuracy in Nanometer CMOS (M P Flynn et al.); Self-Induced Noise in Integrated Circuits (R Gharpurey & S Naraghi); High-Speed Oversampling Analog-to-Digital Converters (A Gharbiya et al.); Designing LC VCOs Using Capacitive Degeneration Techniques (B Jung & R Harjani); Fully Integrated Frequency Synthesizers: A Tutorial (S T Moon et al.); Recent Advances and Design Trends in CMOS Radio Frequency Integrated Circuits (D J Allstot et al.); Equalizers for High-Speed Serial Links (P K Hanumolu et al.); Low-Power, Parallel Interface with Continuous-Time Adaptive Passive Equalizer and Crosstalk Cancellation (C P Yue et al.). Readership: Technologists, scientists, and engineers in the field of high-speed communication circuits. It can also be used as a textbook for graduate and advanced undergraduate courses.
Book Synopsis Techniques for High-performance Digital Frequency Synthesis and Phase Control by : Chun-Ming Hsu (Ph. D.)
Download or read book Techniques for High-performance Digital Frequency Synthesis and Phase Control written by Chun-Ming Hsu (Ph. D.) and published by . This book was released on 2008 with total page 190 pages. Available in PDF, EPUB and Kindle. Book excerpt: This thesis presents a 3.6-GHz, 500-kHz bandwidth digital [delta][sigma] frequency synthesizer architecture that leverages a recently invented noise-shaping time-to-digital converter (TDC) and an all-digital quantization noise cancellation technique to achieve excellent in-band and out-of-band phase noise, respectively. In addition, a passive digital-to-analog converter (DAC) structure is proposed as an efficient interface between the digital loop filter and a conventional hybrid voltage-controlled oscillator (VCO) to create a digitally-controlled oscillator (DCO). An asynchronous divider structure is presented which lowers the required TDC range and avoids the divide-value-dependent delay variation. The prototype is implemented in a 0.13-am CMOS process and its active area occupies 0.95 mm2. Operating under 1.5 V, the core parts, excluding the VCO output buffer, dissipate 26 mA. Measured phase noise at 3.67 GHz achieves -108 dBc/Hz and -150 dBc/Hz at 400 kHz and 20 MHz, respectively. Integrated phase noise at this carrier frequency yields 204 fs of jitter (measured from 1 kHz to 40 MHz). In addition, a 3.2-Gb/s delay-locked loop (DLL) in a 0.18-[mu]m CMOS for chip-tochip communications is presented. By leveraging the fractional-N synthesizer technique, this architecture provides a digitally-controlled delay adjustment with a fine resolution and infinite range. The provided delay resolution is less sensitive to the process, voltage, and temperature variations than conventional techniques. A new [delta][sigma] modulator enables a compact and low-power implementation of this architecture. A simple bang-bang detector is used for phase detection. The prototype operates at a 1.8-V supply voltage with a current consumption of 55 mA. The phase resolution and differential rms clock jitter are 1.4 degrees and 3.6 ps, respectively.
Book Synopsis Low Phase Noise, High Bandwidth Frequency Synthesis Techniques by : Scott Edward Meninger
Download or read book Low Phase Noise, High Bandwidth Frequency Synthesis Techniques written by Scott Edward Meninger and published by . This book was released on 2005 with total page 249 pages. Available in PDF, EPUB and Kindle. Book excerpt: A quantization noise reduction technique is proposed that allows fractional-N frequency synthesizers to achieve high closed loop bandwidth and low output phase noise simultaneously. Quantization induced phase noise is the bottleneck in state-of-the-art synthesizer design, and results in a noise-bandwidth tradeoff that typically limits closed loop synthesizer bandwidths to be
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