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Author : Daniel Georges Saab
Publisher :
ISBN 13 :
Total Pages : 122 pages
Book Rating : 4.:/5 (137 download)
Download or read book Symbolic Switch-level Logic and Fault Simulation of MOS VLSI Circuit written by Daniel Georges Saab and published by . This book was released on 1985 with total page 122 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Author : Vasant B. Rao
Publisher : Springer Science & Business Media
ISBN 13 : 1461317096
Total Pages : 218 pages
Book Rating : 4.4/5 (613 download)
Download or read book Switch-Level Timing Simulation of MOS VLSI Circuits written by Vasant B. Rao and published by Springer Science & Business Media. This book was released on 2012-12-06 with total page 218 pages. Available in PDF, EPUB and Kindle. Book excerpt: Only two decades ago most electronic circuits were designed with a slide-rule, and the designs were verified using breadboard techniques. Simulation tools were a research curiosity and in general were mistrusted by most designers and test engineers. In those days the programs were not user friendly, models were inadequate, and the algorithms were not very robust. The demand for simulation tools has been driven by the increasing complexity of integrated circuits and systems, and it has been aided by the rapid decrease in the cost of com puting that has occurred over the past several decades. Today a wide range of tools exist for analYSiS, deSign, and verification, and expert systems and synthesis tools are rapidly emerging. In this book only one aspect of the analysis and design process is examined. but it is a very important aspect that has received much attention over the years. It is the problem of accurate circuit and timing simulation.
Author : Evstratios Vandris
Publisher :
ISBN 13 :
Total Pages : 304 pages
Book Rating : 4.:/5 (319 download)
Download or read book Switch-level Fault Simulation of MOS VLSI Circuits written by Evstratios Vandris and published by . This book was released on 1991 with total page 304 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Author : Michael D. Schuster
Publisher :
ISBN 13 :
Total Pages : 134 pages
Book Rating : 4.:/5 (256 download)
Download or read book Switch-level Fault Simulation of MOS Digital Circuits written by Michael D. Schuster and published by . This book was released on 1984 with total page 134 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Author : Terry Ping-Chung Lee
Publisher :
ISBN 13 :
Total Pages : 116 pages
Book Rating : 4.:/5 (246 download)
Download or read book A Switch-level Concurrent Fault Simulator for MOS Circuits written by Terry Ping-Chung Lee and published by . This book was released on 1991 with total page 116 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Author : Jeong-Taek Kong
Publisher : Springer Science & Business Media
ISBN 13 : 1461523214
Total Pages : 276 pages
Book Rating : 4.4/5 (615 download)
Download or read book Digital Timing Macromodeling for VLSI Design Verification written by Jeong-Taek Kong and published by Springer Science & Business Media. This book was released on 2012-12-06 with total page 276 pages. Available in PDF, EPUB and Kindle. Book excerpt: Digital Timing Macromodeling for VLSI Design Verification first of all provides an extensive history of the development of simulation techniques. It presents detailed discussion of the various techniques implemented in circuit, timing, fast-timing, switch-level timing, switch-level, and gate-level simulation. It also discusses mixed-mode simulation and interconnection analysis methods. The review in Chapter 2 gives an understanding of the advantages and disadvantages of the many techniques applied in modern digital macromodels. The book also presents a wide variety of techniques for performing nonlinear macromodeling of digital MOS subcircuits which address a large number of shortcomings in existing digital MOS macromodels. Specifically, the techniques address the device model detail, transistor coupling capacitance, effective channel length modulation, series transistor reduction, effective transconductance, input terminal dependence, gate parasitic capacitance, the body effect, the impact of parasitic RC-interconnects, and the effect of transmission gates. The techniques address major sources of errors in existing macromodeling techniques, which must be addressed if macromodeling is to be accepted in commercial CAD tools by chip designers. The techniques presented in Chapters 4-6 can be implemented in other macromodels, and are demonstrated using the macromodel presented in Chapter 3. The new techniques are validated over an extremely wide range of operating conditions: much wider than has been presented for previous macromodels, thus demonstrating the wide range of applicability of these techniques.
Author : Thomas Stephen Messerges
Publisher :
ISBN 13 :
Total Pages : 186 pages
Book Rating : 4.:/5 (211 download)
Download or read book A Novel Switch-level Logic Simulator for VLSI MOS Circuits written by Thomas Stephen Messerges and published by . This book was released on 1989 with total page 186 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Author : M. Bushnell
Publisher : Springer Science & Business Media
ISBN 13 : 0306470403
Total Pages : 690 pages
Book Rating : 4.3/5 (64 download)
Download or read book Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits written by M. Bushnell and published by Springer Science & Business Media. This book was released on 2006-04-11 with total page 690 pages. Available in PDF, EPUB and Kindle. Book excerpt: The modern electronic testing has a forty year history. Test professionals hold some fairly large conferences and numerous workshops, have a journal, and there are over one hundred books on testing. Still, a full course on testing is offered only at a few universities, mostly by professors who have a research interest in this area. Apparently, most professors would not have taken a course on electronic testing when they were students. Other than the computer engineering curriculum being too crowded, the major reason cited for the absence of a course on electronic testing is the lack of a suitable textbook. For VLSI the foundation was provided by semiconductor device techn- ogy, circuit design, and electronic testing. In a computer engineering curriculum, therefore, it is necessary that foundations should be taught before applications. The field of VLSI has expanded to systems-on-a-chip, which include digital, memory, and mixed-signalsubsystems. To our knowledge this is the first textbook to cover all three types of electronic circuits. We have written this textbook for an undergraduate “foundations” course on electronic testing. Obviously, it is too voluminous for a one-semester course and a teacher will have to select from the topics. We did not restrict such freedom because the selection may depend upon the individual expertise and interests. Besides, there is merit in having a larger book that will retain its usefulness for the owner even after the completion of the course. With equal tenacity, we address the needs of three other groups of readers.
Author : Carnegie-Mellon University. SRC-CMU Research Center for Computer-Aided Design
Publisher :
ISBN 13 :
Total Pages : 6 pages
Book Rating : 4.:/5 (123 download)
Download or read book Test Pattern Generation for Sequential MOS Circuits by Symbolic Fault Simulation written by Carnegie-Mellon University. SRC-CMU Research Center for Computer-Aided Design and published by . This book was released on 1989 with total page 6 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Author : Kyeongsoon Cho
Publisher :
ISBN 13 :
Total Pages : 129 pages
Book Rating : 4.:/5 (16 download)
Download or read book Test pattern generation for combinatorial and sequential MOS circuits by symbolic fault simulation written by Kyeongsoon Cho and published by . This book was released on 1988 with total page 129 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Author : Vasant Bangalore Rao
Publisher :
ISBN 13 :
Total Pages : 476 pages
Book Rating : 4.:/5 (227 download)
Download or read book Switch-level Timing Simulation of MOS VLSI Circuits written by Vasant Bangalore Rao and published by . This book was released on 1985 with total page 476 pages. Available in PDF, EPUB and Kindle. Book excerpt: This report deals with the development of a fast and accurate simulation tool for very-large-scale integrated (VLSI) circuits consisting of metal-oxide-semiconductor (MOS) transistors. Such tools are called switch-level timing simulators and they provide adequate information on the performance of the circuits with a reasonable expenditure of computation time even for very large circuits. The algorithms presented in this thesis can handle only n-channel MOS(NMOS) circuits, but are easily extendible to handle complementary MOS(CMOS) circuits as well. The algorithms presented in this report have been implemented in a computer program called MOSTIM. In all the circuits simulated thus far, MOSTIM provides timing information with an accuracy of within 10% of that provided by SPICE2, at approximately two orders of magnitude faster in simulation speed. (Author).
Author : Ravi K. Gulati
Publisher : Springer Science & Business Media
ISBN 13 : 1461531462
Total Pages : 121 pages
Book Rating : 4.4/5 (615 download)
Download or read book IDDQ Testing of VLSI Circuits written by Ravi K. Gulati and published by Springer Science & Business Media. This book was released on 2012-12-06 with total page 121 pages. Available in PDF, EPUB and Kindle. Book excerpt: Power supply current monitoring to detect CMOS IC defects during production testing quietly laid down its roots in the mid-1970s. Both Sandia Labs and RCA in the United States and Philips Labs in the Netherlands practiced this procedure on their CMOS ICs. At that time, this practice stemmed simply from an intuitive sense that CMOS ICs showing abnormal quiescent power supply current (IDDQ) contained defects. Later, this intuition was supported by data and analysis in the 1980s by Levi (RACD, Malaiya and Su (SUNY-Binghamton), Soden and Hawkins (Sandia Labs and the University of New Mexico), Jacomino and co-workers (Laboratoire d'Automatique de Grenoble), and Maly and co-workers (Carnegie Mellon University). Interest in IDDQ testing has advanced beyond the data reported in the 1980s and is now focused on applications and evaluations involving larger volumes of ICs that improve quality beyond what can be achieved by previous conventional means. In the conventional style of testing one attempts to propagate the logic states of the suspended nodes to primary outputs. This is done for all or most nodes of the circuit. For sequential circuits, in particular, the complexity of finding suitable tests is very high. In comparison, the IDDQ test does not observe the logic states, but measures the integrated current that leaks through all gates. In other words, it is like measuring a patient's temperature to determine the state of health. Despite perceived advantages, during the years that followed its initial announcements, skepticism about the practicality of IDDQ testing prevailed. The idea, however, provided a great opportunity to researchers. New results on test generation, fault simulation, design for testability, built-in self-test, and diagnosis for this style of testing have since been reported. After a decade of research, we are definitely closer to practice.
Author :
Publisher :
ISBN 13 :
Total Pages : 638 pages
Book Rating : 4.3/5 (91 download)
Download or read book Proceedings written by and published by . This book was released on 1991 with total page 638 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Author : Larry G. Jones
Publisher :
ISBN 13 :
Total Pages : 34 pages
Book Rating : 4.:/5 (31 download)
Download or read book Incremental Zero/ Unit-delay Switch-level Logic Simulation written by Larry G. Jones and published by . This book was released on 1990 with total page 34 pages. Available in PDF, EPUB and Kindle. Book excerpt: Abstract: "We present the methods used in the implementation of an incremental zero/unit-delay switch-level logic simulator for MOS circuits based on the MOSSIM II switch-level model. The incremental simulator is embedded within a single fully-integrated capture/compile/simulate tool. Modifications to the design at any level in the structural design hierarchy are automatically mapped into changes in the underlying transistor netlist and the incremental simulator is triggered to quickly resimulate only those regions of the circuit whose behavior has been modified by the change."
Author : Sharad C. Seth
Publisher :
ISBN 13 :
Total Pages : 102 pages
Book Rating : 4.F/5 ( download)
Download or read book Tutorial, Test Generation for VLSI Circuits written by Sharad C. Seth and published by . This book was released on 1987 with total page 102 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Author : Kyeongsoon Cho
Publisher :
ISBN 13 :
Total Pages : 124 pages
Book Rating : 4.:/5 (256 download)
Download or read book Test pattern generation for combinational and sequential MOS circuits by symbolic fault simulation written by Kyeongsoon Cho and published by . This book was released on 1989 with total page 124 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Author : Guoyong Shi
Publisher : Springer
ISBN 13 : 1493911031
Total Pages : 308 pages
Book Rating : 4.4/5 (939 download)
Download or read book Advanced Symbolic Analysis for VLSI Systems written by Guoyong Shi and published by Springer. This book was released on 2014-06-19 with total page 308 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book provides comprehensive coverage of the recent advances in symbolic analysis techniques for design automation of nanometer VLSI systems. The presentation is organized in parts of fundamentals, basic implementation methods and applications for VLSI design. Topics emphasized include statistical timing and crosstalk analysis, statistical and parallel analysis, performance bound analysis and behavioral modeling for analog integrated circuits. Among the recent advances, the Binary Decision Diagram (BDD) based approaches are studied in depth. The BDD-based hierarchical symbolic analysis approaches, have essentially broken the analog circuit size barrier.
