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Leakage Power Analysis And Optimization In Deep Submicron Technologies Under Process Variation
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Book Synopsis Leakage Power Analysis and Optimization in Deep-Submicron Technologies Under Process Variation by : Saumil S. Shah
Download or read book Leakage Power Analysis and Optimization in Deep-Submicron Technologies Under Process Variation written by Saumil S. Shah and published by . This book was released on 2007 with total page 282 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis Stochastic Process Variation in Deep-Submicron CMOS by : Amir Zjajo
Download or read book Stochastic Process Variation in Deep-Submicron CMOS written by Amir Zjajo and published by Springer Science & Business Media. This book was released on 2013-11-19 with total page 207 pages. Available in PDF, EPUB and Kindle. Book excerpt: One of the most notable features of nanometer scale CMOS technology is the increasing magnitude of variability of the key device parameters affecting performance of integrated circuits. The growth of variability can be attributed to multiple factors, including the difficulty of manufacturing control, the emergence of new systematic variation-generating mechanisms, and most importantly, the increase in atomic-scale randomness, where device operation must be described as a stochastic process. In addition to wide-sense stationary stochastic device variability and temperature variation, existence of non-stationary stochastic electrical noise associated with fundamental processes in integrated-circuit devices represents an elementary limit on the performance of electronic circuits. In an attempt to address these issues, Stochastic Process Variation in Deep-Submicron CMOS: Circuits and Algorithms offers unique combination of mathematical treatment of random process variation, electrical noise and temperature and necessary circuit realizations for on-chip monitoring and performance calibration. The associated problems are addressed at various abstraction levels, i.e. circuit level, architecture level and system level. It therefore provides a broad view on the various solutions that have to be used and their possible combination in very effective complementary techniques for both analog/mixed-signal and digital circuits. The feasibility of the described algorithms and built-in circuitry has been verified by measurements from the silicon prototypes fabricated in standard 90 nm and 65 nm CMOS technology.
Book Synopsis Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation by : Nadine Azemard
Download or read book Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation written by Nadine Azemard and published by Springer Science & Business Media. This book was released on 2007-08-21 with total page 595 pages. Available in PDF, EPUB and Kindle. Book excerpt: This volume features the refereed proceedings of the 17th International Workshop on Power and Timing Modeling, Optimization and Simulation. Papers cover high level design, low power design techniques, low power analog circuits, statistical static timing analysis, power modeling and optimization, low power routing optimization, security and asynchronous design, low power applications, modeling and optimization, and more.
Book Synopsis Estimation and Optimization of Leakage Power in the Presence of Process Variations by : Romana Fernandes
Download or read book Estimation and Optimization of Leakage Power in the Presence of Process Variations written by Romana Fernandes and published by . This book was released on 2010 with total page 86 pages. Available in PDF, EPUB and Kindle. Book excerpt: With the increasing importance of run-time leakage power dissipation (around 55% of total power), it has become necessary to accurately estimate it not only as a function of input vectors, but also as a function of process parameters. In this work, the importance of considering the effects of process parameter variations for the accurate estimation of leakage power is emphasized and supported by experimental results. Leakage power corresponding to the maximum vector presents itself as a higher bound for run-time leakage and is a measure of reliability. This problem is addressed and a heuristic is developed and implemented to accurately estimate the probabilistic distribution of the maximum run-time leakage power in the presence of variations in process parameters such as threshold voltage, critical dimensions and doping concentration. Both sub-threshold and gate leakage current have been considered. A heuristic approach is proposed to determine the vector that causes the maximum leakage power under the influence of random process variations. This vector is then used to estimate the lognormal distribution of the total leakage current of the circuit by summing up the lognormal leakage current distributions of the individual standard cells at their respective input levels. The proposed method has been effective in accurately estimating the leakage mean, standard deviation and probability density function of ISCAS-85 benchmark circuits. Run-time leakage power is becoming a dominant component of the total power consumption of a CMOS circuit. A fast and accurate method for the estimation of average run-time leakage power using input signal probabilities is implemented. The proposed method considers signal correlations due to re-convergent fanout nodes and process variations to improve the accuracy. The heuristic developed, estimates the average leakage power distribution by computing the mean and standard deviation. This heuristic was tested on ISCAS-85 benchmark circuits and was verified for accuracy. An optimization technique to minimize the average run-time leakage power using a dual threshold voltage approach is implemented. The low leakage variability of high threshold devices helps reduce the high variability of nominal threshold devices and makes leakage reduction possible to a large extent. A significant improvement was seen for mean and standard deviation when tested on ISCAS-85 benchmark circuits.
Book Synopsis Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation by : Rene van Leuken
Download or read book Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation written by Rene van Leuken and published by Springer Science & Business Media. This book was released on 2011-02-04 with total page 270 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book constitutes the refereed proceedings of the 20th International Conference on Integrated Circuit and System Design, PATMOS 2010, held in Grenoble, France, in September 2010. The 24 revised full papers presented and the 9 extended abstracts were carefully reviewed and are organized in topical sections on design flows; circuit techniques; low power circuits; self-timed circuits; process variation; high-level modeling of poweraware heterogeneous designs in SystemC-AMS; and minalogic.
Book Synopsis Power Optimization in Deep Submicron Technology by : Pradeep Jayaramu
Download or read book Power Optimization in Deep Submicron Technology written by Pradeep Jayaramu and published by . This book was released on 2008 with total page 188 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis Statistical Performance Analysis and Modeling Techniques for Nanometer VLSI Designs by : Ruijing Shen
Download or read book Statistical Performance Analysis and Modeling Techniques for Nanometer VLSI Designs written by Ruijing Shen and published by Springer Science & Business Media. This book was released on 2014-07-08 with total page 326 pages. Available in PDF, EPUB and Kindle. Book excerpt: Since process variation and chip performance uncertainties have become more pronounced as technologies scale down into the nanometer regime, accurate and efficient modeling or characterization of variations from the device to the architecture level have become imperative for the successful design of VLSI chips. This book provides readers with tools for variation-aware design methodologies and computer-aided design (CAD) of VLSI systems, in the presence of process variations at the nanometer scale. It presents the latest developments for modeling and analysis, with a focus on statistical interconnect modeling, statistical parasitic extractions, statistical full-chip leakage and dynamic power analysis considering spatial correlations, statistical analysis and modeling for large global interconnects and analog/mixed-signal circuits. Provides readers with timely, systematic and comprehensive treatments of statistical modeling and analysis of VLSI systems with a focus on interconnects, on-chip power grids and clock networks, and analog/mixed-signal circuits; Helps chip designers understand the potential and limitations of their design tools, improving their design productivity; Presents analysis of each algorithm with practical applications in the context of real circuit design; Includes numerical examples for the quantitative analysis and evaluation of algorithms presented. Provides readers with timely, systematic and comprehensive treatments of statistical modeling and analysis of VLSI systems with a focus on interconnects, on-chip power grids and clock networks, and analog/mixed-signal circuits; Helps chip designers understand the potential and limitations of their design tools, improving their design productivity; Presents analysis of each algorithm with practical applications in the context of real circuit design; Includes numerical examples for the quantitative analysis and evaluation of algorithms presented.
Book Synopsis Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation by : Vassilis Paliouras
Download or read book Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation written by Vassilis Paliouras and published by Springer Science & Business Media. This book was released on 2005-09-06 with total page 767 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book constitutes the refereed proceedings of the 15th International Workshop on Power and Timing Optimization and Simulation, PATMOS 2005, held in Leuven, Belgium in September 2005. The 74 revised full papers presented were carefully reviewed and selected from numerous submissions. The papers are organized in topical sections on low-power processors, code optimization for low-power, high-level design, telecommunications and signal processing, low-power circuits, system-on-chip design, busses and interconnections, modeling, design automation, low-power techniques, memory and register files, applications, digital circuits, and analog and physical design.
Book Synopsis Low-Power VLSI Circuits and Systems by : Ajit Pal
Download or read book Low-Power VLSI Circuits and Systems written by Ajit Pal and published by Springer. This book was released on 2014-11-17 with total page 417 pages. Available in PDF, EPUB and Kindle. Book excerpt: The book provides a comprehensive coverage of different aspects of low power circuit synthesis at various levels of design hierarchy; starting from the layout level to the system level. For a seamless understanding of the subject, basics of MOS circuits has been introduced at transistor, gate and circuit level; followed by various low-power design methodologies, such as supply voltage scaling, switched capacitance minimization techniques and leakage power minimization approaches. The content of this book will prove useful to students, researchers, as well as practicing engineers.
Book Synopsis Electronic Design Automation for IC Implementation, Circuit Design, and Process Technology by : Luciano Lavagno
Download or read book Electronic Design Automation for IC Implementation, Circuit Design, and Process Technology written by Luciano Lavagno and published by CRC Press. This book was released on 2017-02-03 with total page 893 pages. Available in PDF, EPUB and Kindle. Book excerpt: The second of two volumes in the Electronic Design Automation for Integrated Circuits Handbook, Second Edition, Electronic Design Automation for IC Implementation, Circuit Design, and Process Technology thoroughly examines real-time logic (RTL) to GDSII (a file format used to transfer data of semiconductor physical layout) design flow, analog/mixed signal design, physical verification, and technology computer-aided design (TCAD). Chapters contributed by leading experts authoritatively discuss design for manufacturability (DFM) at the nanoscale, power supply network design and analysis, design modeling, and much more. New to This Edition: Major updates appearing in the initial phases of the design flow, where the level of abstraction keeps rising to support more functionality with lower non-recurring engineering (NRE) costs Significant revisions reflected in the final phases of the design flow, where the complexity due to smaller and smaller geometries is compounded by the slow progress of shorter wavelength lithography New coverage of cutting-edge applications and approaches realized in the decade since publication of the previous edition—these are illustrated by new chapters on 3D circuit integration and clock design Offering improved depth and modernity, Electronic Design Automation for IC Implementation, Circuit Design, and Process Technology provides a valuable, state-of-the-art reference for electronic design automation (EDA) students, researchers, and professionals.
Book Synopsis A Novel Dynamic Power Cutoff Technology (DPCT) for Active Leakage Reduction in Deep Submicron VLSI CMOS Circuits by :
Download or read book A Novel Dynamic Power Cutoff Technology (DPCT) for Active Leakage Reduction in Deep Submicron VLSI CMOS Circuits written by and published by . This book was released on 2007 with total page 101 pages. Available in PDF, EPUB and Kindle. Book excerpt: Due to the exponential increase of subthreshold and gate leakage currents with technology scaling, leakage power is increasingly significant in CMOS circuits as the technology scales down. The leakage power is as much as 50% of the total power in the 90nm technology and is becoming dominant in more advanced CMOS technologies with smaller feature sizes. Also, the leakage in active mode is significantly larger due to the higher die temperature in active mode. Although many leakage reduction techniques have been proposed, most of them can only reduce the circuit leakage power in standby mode. In this thesis, we present a novel active leakage power reduction technique using dynamic power cutoff, called the dynamic power cutoff technique (DPCT). To reduce the active leakage power, we target the idle part of the circuit when it is in active mode. First, the switching window for each gate, during which a gate makes its transitions, is identified by static timing analysis. Then, the circuit is optimally partitioned into different groups based on the minimal switching window (MSW) of each gate. Finally, power cutoff transistors are inserted into each group to control the power connections of that group. The power of each gate is only turned on during a small timing window within each clock cycle, which results in significant active leakage power savings. Standby leakage can also be reduced by turning off the power connections of all gates all of the time once the circuit is idle. This technique also reduces dynamic power and short-circuit power by reducing the circuit glitches. Experimental results on ISCAS '85 benchmark circuits at the logic level modeled using 70nm Berkeley Predictive Models show up to 90% of active leakage, 99% of standby leakage, up to 54% of dynamic, and up to 72% of total power savings. DPCT can also reduce the maximal voltage drop on the power grid by more than 30% on average. With process variations, the average total power and active leakage power savings will be reduced by 12.7% and 14.8%, respectively. In spite of that, DPCT still gives excellent power savings, which are 73.6% of active leakage power and 34.7% of total power under process variations. We also implemented the layouts of a 16-bit multiplier and a c432 using DPCT. The experimental results for the layout designs confirmed the effectiveness of DPCT in physical level design.
Book Synopsis Integrated Circuit and System Design by : Enrico Macii
Download or read book Integrated Circuit and System Design written by Enrico Macii and published by Springer. This book was released on 2004-08-24 with total page 926 pages. Available in PDF, EPUB and Kindle. Book excerpt: WelcometotheproceedingsofPATMOS2004,thefourteenthinaseriesofint- national workshops. PATMOS 2004 was organized by the University of Patras with technical co-sponsorship from the IEEE Circuits and Systems Society. Over the years, the PATMOS meeting has evolved into an important - ropean event, where industry and academia meet to discuss power and timing aspects in modern integrated circuit and system design. PATMOS provides a forum for researchers to discuss and investigate the emerging challenges in - sign methodologies and tools required to develop the upcoming generations of integrated circuits and systems. We realized this vision this year by providing a technical program that contained state-of-the-art technical contributions, a keynote speech, three invited talks and two embedded tutorials. The technical program focused on timing, performance and power consumption, as well as architectural aspects, with particular emphasis on modelling, design, charac- rization, analysis and optimization in the nanometer era. This year a record 152 contributions were received to be considered for p- sible presentation at PATMOS. Despite the choice for an intense three-day m- ting, only 51 lecture papers and 34 poster papers could be accommodated in the single-track technical program. The Technical Program Committee, with the - sistance of additional expert reviewers, selected the 85 papers to be presented at PATMOS and organized them into 13 technical sessions. As was the case with the PATMOS workshops, the review process was anonymous, full papers were required, and several reviews were received per manuscript.
Book Synopsis Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation by : Johan Vounckx
Download or read book Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation written by Johan Vounckx and published by Springer Science & Business Media. This book was released on 2006-09-08 with total page 691 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book constitutes the refereed proceedings of the 16th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2006. The book presents 41 revised full papers and 23 revised poster papers together with 4 key notes and 3 industrial abstracts. Topical sections include high-level design, power estimation and modeling memory and register files, low-power digital circuits, busses and interconnects, low-power techniques, applications and SoC design, modeling, and more.
Book Synopsis Introduction to VLSI Circuits and Systems by : John P. Uyemura
Download or read book Introduction to VLSI Circuits and Systems written by John P. Uyemura and published by . This book was released on 2002 with total page 668 pages. Available in PDF, EPUB and Kindle. Book excerpt: CD-ROM contains: AIM SPICE (from AIM Software) -- Micro-Cap 6 (from Spectrum Software) -- Silos III Verilog Simulator (from Simucad) -- Adobe Acrobat Reader 4.0 (from Adobe).
Download or read book Proceedings written by and published by . This book was released on 2004 with total page 424 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis Predictive Modeling of Integrated Circuit Manufacturing Variation by : Swamy V. Muddu
Download or read book Predictive Modeling of Integrated Circuit Manufacturing Variation written by Swamy V. Muddu and published by . This book was released on 2007 with total page 190 pages. Available in PDF, EPUB and Kindle. Book excerpt: Continuous scaling of feature sizes in CMOS integrated circuits (IC) pushes the design performance envelope as well as design complexity higher with each successive technology node. Advancements in materials and optics of the manufacturing process enable the scaling and manufacturability of devices in ICs. As device feature dimensions approach the physical limits of lithography and the manufacturing process, the smallest geometric and material variations manifest as design-level performance and power variability. One of the main pathological effects of IC scaling is the increase in design variability as a fraction of performance with each technology node. This design variability directly affects IC parametric (i.e., performance-limited) and catastrophic (i.e., defect-limited) yield, and consequently, IC cost. To address the increase in manufacturing variability in deep-submicron (DSM) technologies and to improve IC yield, a new design for manufacturability (DFM) paradigm has emerged in the recent past. The DFM paradigm encompasses a set of design methodologies that address manufacturing and process non-idealities at the design level to make ICs more robust to variations. DFM is also interpreted as a set of post-layout design fixing techniques that enhance and ease manufacturability. In general, the objective of DFM is to improve IC yield and cost by increasing manufacturing-awareness in the design phase, as well as design-awareness in the manufacturing phase. To achieve this dual objective of DFM, design must be driven by models of variation in the manufacturing process and the manufacturing process, must be made aware of the design intent. Variations in the IC manufacturing process are manifested as (1) deviation from the intended shapes of IC geometries, and (2) variations in impurity (i.e., dopant) concentrations. These variations are composed of systematic and random components. The systematic component of variation can be attributed to specific sources in the manufacturing process, while the random component is usually a result of confounding of several sources of variation and cannot be attributed to specific sources. A significant fraction of the total variation in shapes of IC geometries is systematic in sources such as focus, exposure dose, lens aberrations, etc. The objective of this thesis is to model the impact of the raw sources of variation at the mask making and wafer pattern transfer phases in manufacturing. The primary goal in the associated research is to develop models that can drive systematic variation-aware design. We propose techniques to model the impact of mask-level and wafer-level sources of variation on IC geometries. At the mask-level, proximity effects and resist heating caused by electron-beam writing are the two main sources of mask critical dimension (CD) errors. We propose a novel methodology to model resist heating caused by electron-beam writing on the mask resist. We use the resist heating model to drive temperature-aware mask writing schedules that minimize resist temperature, and consequently minimize mask CD error. Sub-wavelength optical lithography in sub-100nm technology nodes is enabled by resolution enhancement techniques (RETs) that allow patterning of layout features on silicon wafers. Optical proximity correction (OPC) is the most prominent RET used to compensate a design layout for optical and process effects prior to mask making and lithography. OPC modifies the shapes of layout features, and consequently increases mask complexity and cost. We develop a model of post-OPC mask cost of design features, to drive design-aware mask cost optimization. Despite advanced RETs and illumination techniques, several sources of variation in the pattern transfer process result in variations in chip-level performance and power. At 45nm and below, accurate design-level performance and power analyses must consider litho-simulated non-idealities in patterning. However, the simulation of exposure, resist and etch processing steps in lithography is computationally expensive to perform at chip-scale, and essentially infeasible during iterative design optimization. In this thesis, We develop a predictive model of post-OPC linewidth of devices in standard cells across the process window. The predictive model is fast, accurate and highly scalable, enabling its use in the design phase at full-chip scale without actually performing OPC and litho simulation. Last, we demonstrate the use of predictive linewidth models in fast and accurate leakage estimation and optimization. First, We discuss the use of through-focus systematic linewidth models to achieve accurate leakage estimation. We then discuss a novel detailed placement perturbation approach that leverages systematic pitch and focus interactions to improve leakage in light of systematic linewidth variation. These two methods demonstrate the use of predictive models of variation in driving variation-aware design analysis and optimization.
Book Synopsis Statistical Methodologies for Modelling the Impact of Process Variability in Ultra-deep-submicron SRAMs by : Kaya Can Akyel
Download or read book Statistical Methodologies for Modelling the Impact of Process Variability in Ultra-deep-submicron SRAMs written by Kaya Can Akyel and published by . This book was released on 2014 with total page 0 pages. Available in PDF, EPUB and Kindle. Book excerpt: The downscaling of device geometry towards its physical limits exacerbates the impact of the inevitable atomistic phenomena tied to matter granularity. In this context, many different variability sources raise and affect the electrical characteristics of the manufactured devices. The variability-aware design methodology has therefore become a popular research topic in the field of digital circuit design, since the increased number of transistors in the modern integrated circuits had led to a large statistical variability affecting dramatically circuit functionality. Static Random Access Memory (SRAM) circuits which are manufactured with the most aggressive design rules in a given technology node and contain billions of transistor, are severely impacted by the process variability which stands as the main obstacle for the further reduction of the bitcell area and of its minimum operating voltage. The reduction of the latter is a very important parameter for Low-Power design, which is one of the most popular research fields of our era. The optimization of SRAM bitcell design therefore has become a crucial task to guarantee the good functionality of the design at an industrial manufacturing level, in the same time answering to the high density and low power demands. However, the long time required by each new technology node process development means a long waiting time before obtaining silicon results, which is in cruel contrast with the fact that the design optimization has to be started as early as possible. An efficient SPICE characterization methodology for the minimum operating voltage of SRAM circuits is therefore a mandatory requirement for design optimization. This research work concentrates on the development of the new simulation methodologies for the modeling of the process variability in ultra-deep-submicron SRAMs, with the ultimate goal of a significantly accurate modeling of the minimum operating voltage Vmin. A particular interest is also carried on the time-dependent sub-class of the process variability, which appears as a change in the electrical characteristics of a given transistor during its operation and during its life-time. This research work has led to many publications and one patent application. The majority of findings are retained by STMicroelectronics SRAM development team for a further use in their design optimization flow.
