Author : Saeroonter Oh
Publisher : Stanford University
ISBN 13 :
Total Pages : 147 pages
Book Rating : 4.F/5 ( download)
Book Synopsis Modeling of III-V Nanoscale Field-effect Transistors for Logic Circuits by : Saeroonter Oh
Download or read book Modeling of III-V Nanoscale Field-effect Transistors for Logic Circuits written by Saeroonter Oh and published by Stanford University. This book was released on 2010 with total page 147 pages. Available in PDF, EPUB and Kindle. Book excerpt: As silicon CMOS technology continues to scale down its minimum critical dimension, it becomes increasingly difficult to enhance device switching speed due to fundamental limitations. Innovations in device structure and materials are pursued to accommodate improvement in performance as well as reduction in transistor size. For beyond-22-nm CMOS technology, III-V channel FETs are considered as a compelling candidate for extending the device scaling limit of low-power and high-speed operation, owing to their superb carrier transport properties and recent experimental advancements. In this thesis, device simulation, compact modeling, circuit design, circuit performance assessment and estimation of III-V logic transistors are carried out to study key considerations such as device pitch, parasitics, and the importance of PMOS for circuit-level performance. To effectively connect device characteristics with circuit design, a physics-based compact model for digital logic is constructed. The model encompasses effects such as field-confined and spatially-confined trapezoidal quantum well sub-band energies, gate leakage tunneling current and parasitic capacitance. The developed compact model contains only three fitting parameters and is verified by experiment and circuit simulations. The compact model enables other bodies of work for the purpose of circuit-level design and performance estimation. To demonstrate the capability of the model in a circuit environment we apply the compact model to composite circuits such as FO4 inverter chains and SRAM cache to evaluate and project performance and power trends for beyond-22-nm technology.