Author : Aishwariya Pattabiraman
Publisher :
ISBN 13 :
Total Pages : 80 pages
Book Rating : 4.:/5 (776 download)
Book Synopsis Heterogeneous Cache Architecture in Network-on-chips by : Aishwariya Pattabiraman
Download or read book Heterogeneous Cache Architecture in Network-on-chips written by Aishwariya Pattabiraman and published by . This book was released on 2011 with total page 80 pages. Available in PDF, EPUB and Kindle. Book excerpt: Current trends in multicore research suggest that hundreds of cores will be integrated on a single chip in the future for high performance. Increasing the number of cores increases execution speed. However, performance of the system also depends on the cache access speed. Several ideas have been suggested for the cache management in multicore systems. The wire delay in large unified on-chip caches and the need for higher bandwidth have made banked caches connected by two dimensional switched network the choice for the last level cache organization. In the NoC structure accessing nearby cache banks is faster than accessing remote banks. Hence it is called Non-Uniform Cache Architecture (NUCA). In NUCA since the cache access latency depends on the cache bank that is accessed, we need to find efficient methods to place data in the cache banks close to the accessing core. Data migration methods migrate data lines to the cache banks close to the accessing cores during their runtime. However, good initial data placement methods are necessary to achieve low cache access times. They can be used along with the existing data migration schemes. Many software techniques like locality aware data placement and management of cache capacity allocation between processes have been suggested in literature. However, they fail to take advantage of the physical distribution of last level cache among the tiles. Much less has been done to combine both hardware and software techniques to reduce the cache access latency. In this thesis, we have shown that equal distribution of the cache among the tiles in NoCs may not be the optimal cache distribution for all workloads. Therefore we propose static heterogeneous cache architecture for multi-programmed workloads. The heterogeneity and the appropriate scheduling by the OS will help to reduce network hops by placing more cache blocks close to the cores executing data intensive process. Furthermore, we also propose dynamic heterogeneous cache architecture for multi-threaded workloads. In multi-threaded workloads, data lines are shared by a number of cores. Initial placement of the shared data lines close to one of the accessing cores may lead to higher access times for other cores. Also, the optimal cache configuration varies depending on how the data is shared between processes in each workload. These aspects are considered in this work to formulate the page coloring and cache allocation as a placement problem. A constructive heuristic has been presented which gives the optimal cache configuration and page coloring for each workload. Both static and dynamic cache configuration exploit the underlying architecture and existing OS level software policies to provide lower cache access latencies for future CMPs. Finally, both of these methods are scalable and suit future workloads effectively.
