Author :
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ISBN 13 :
Total Pages : 85 pages
Book Rating : 4.:/5 (651 download)
Book Synopsis Hardware Implementation of Genetic Algorithm Modules for Intelligent Systems by :
Download or read book Hardware Implementation of Genetic Algorithm Modules for Intelligent Systems written by and published by . This book was released on 2005 with total page 85 pages. Available in PDF, EPUB and Kindle. Book excerpt: A Genetic Algorithm (GA) is an intelligent search strategy supported by operations inspired by biological evolution. A typical GA for a particular application is a robust optimization algorithm that mimics the Darwinian theory of evolution. Although a GA is able to find very good solutions for a variety of applications, it typically requires many computations and iterations to be effective, and the amount of time consumed by these computations and iterations is enormous. Thus, software implementations of GAs applied to increasingly complex problems and large search spaces can cause unacceptable delays. An alternative to this approach is the hardware implementation of GAs in order to achieve tremendous speedup over software counterparts by exploiting the inherent parallelism of the GA paradigm. This thesis presents the design of libraries of hardware modules for a GA system - one library in the Hardware Description Language (HDL) Verilog HDL and one in the language VHDL. Each library is based on a widely used MATLAB library. The different modules of the GA system, i.e., selection modules (roulette wheel selection), crossover modules (one-point crossover, two-point crossover, arithmetic crossover, uniform crossover), the mutation module, example fitness modules and the random number generators are described in hardware using the HDLs. These Verilog HDL and VHDL RTL models are simulated to check for functionality and performance. The HDL modules can be used by other researchers to implement GAs in hardware. In this work the modules are also incorporated into an example GA architecture which exploits the features of pipelining and parallelization. These hardware modules can be synthesized to obtain the gate-level netlist and can be further mapped to Application Specific Integrated Circuits (ASICs) and Field Programmable Gate Arrays (FPGAs). The HDL simulation results and performance analysis for the GA architectures for several example problems are presented here and these results are compared to similar GAs implemented in software and in problem-specific custom hardware architectures. The modules in the library can be used by researchers to implement efficient architectures for specific problems of interest.
