Author : Zhenshan Xie (Software engineer)
Publisher :
ISBN 13 :
Total Pages : 0 pages
Book Rating : 4.:/5 (135 download)
Book Synopsis Efficient Hardware Implementation Architectures for Generalized Integrated Interleaved Decoder by : Zhenshan Xie (Software engineer)
Download or read book Efficient Hardware Implementation Architectures for Generalized Integrated Interleaved Decoder written by Zhenshan Xie (Software engineer) and published by . This book was released on 2022 with total page 0 pages. Available in PDF, EPUB and Kindle. Book excerpt: Generalized integrated interleaved (GII) codes are advanced error-correcting codes. They nest Reed-Solomon (RS) or BCH sub-codewords to generate more powerful RS or BCH codewords. The hyper-speed decoding and good error-correction capability make GII codes one of the best candidates for next-generation terabit/s digital storage and communications. However, the hardware architecture design for GII decoder faces many challenges. Above all, the key equation solving (KES) in the nested decoding stage causes clock frequency bottleneck and takes a large portion of the GII decoder area. Besides, short GII-BCH codes are required for new fast storage class memories (SCMs), which pose new issues for the GII-BCH decoder design. Many techniques have been developed in this dissertation to eliminate the implementation bottlenecks for almost every decoding step in the decoder architecture design, especially for the nested KES. Major contributions include: i) an efficient nested KES algorithm and architecture to eliminate the clock frequency bottleneck and substantially reduce the area complexity; ii) a scaled nested KES algorithm and architecture to further reduce the area complexity by scaling polynomials to enable product term sharing; iii) a fast nested KES algorithm and architecture to break data dependency to truly reduce the critical path to one multiplier and several adders/multiplexers and hence reduce the nested KES latency almost by half; iv) a scaled fast nested KES algorithm and architecture to further reduce the area complexity while keeping only one multiplier and several adders/multiplexers in the critical path; and v) a scheme to reduce the number of processing elements without undesirable degradation on the error-correcting performance. Compared to GII-RS decoding, the nested KES design for GII-BCH decoding is more challenging, since two instead of one higher-order syndromes need to be incorporated and every other iteration needs to be skipped. Efficient nested KES designs for GII-BCH codes have also been developed by algorithmic reformulations. For the overall GII decoder, the proposed designs can achieve more than 320Gb/s throughput with only 7 gates in the critical path. Several effective schemes have also been proposed to address the issues for applying GII-BCH codes to the new fast SCM applications, where short codes with low redundancy and high correction capability are required. In this case, the error correction capabilities of the sub- and nested codewords of the GII-BCH codes are relatively small, leading to issues regarding the KES throughput/latency and decoding miscorrections. i) A high-throughput sub-word KES was developed to directly compute the polynomials and variables for 3-error-correcting decoding. Utilizing the properties of the involved variables and syndromes, reformulations were developed to enable product term sharing and hence substantially simplify the polynomial and variable computation. Almost three times throughput with smaller area can be achieved, compared to the best previous design. ii) An efficient nested KES design has been proposed to eliminate the initialization clock from each nested decoding round. The polynomial updating was split and the critical path was reduced to one multiplier and several adders/multiplexers without pre-computing combined scalars. Substantial area saving can be achieved by sharing hardware units for polynomial updating. iii) Three low-complexity methods, i.e., checking nested syndromes, utilizing extended BCH codes, and tracking error locator polynomial degrees, have been proposed to detect and mitigate the miscorrections for the decoding of short GII-BCH codes, and hence the severe performance loss can be almost completely eliminated. iv) The miscorrection mitigation schemes were further optimized and the average nested decoding latency was reduced significantly. v) A sub-word selection strategy and a higher-order syndrome updating scheme were developed to reduce the worst-case nested decoding latency substantially. For an example short GII-BCH code over $GF(2^{10})$ for SCM applications, the performance gap due to miscorrections is closed and low-complexity and low-latency decoding is achieved. In summary, the proposed designs have significant contributions to the GII decoder architecture design, especially the nested KES, and the decoding of short GII-BCH codes. In the future study, the research focus can be on the joint architecture design for other decoder components, more efficient miscorrection mitigating schemes, and concise formulas for performance estimation.
