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Directory Based Wired Wireless Network On Chip Architectures To Improve Performance
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Book Synopsis Directory-based Wired-wireless Network-on-chip Architectures to Improve Performance by : Kishore K. Chidella
Download or read book Directory-based Wired-wireless Network-on-chip Architectures to Improve Performance written by Kishore K. Chidella and published by . This book was released on 2018 with total page 117 pages. Available in PDF, EPUB and Kindle. Book excerpt: Network-on-Chip (NoC) architectures have emerged as a promising technology for modern computer systems to address the design challenges of high-performance computing systems. Wireless NoC (WNoC) architectures are introduced to improve performance by reducing the core-to-core communication latency. Conventional WNoCs broadcast messages that increase bandwidth-traffic, communication latency, and power consumption. Studies show that directory-based schemes have potential to reduce bandwidth-traffic and improve performance. This work introduces a WNoC architecture with centralized directory (WNoC-CD) and a WNoC architecture with distributed directories (WNoC-DDs) to enhance faster execution by reducing bandwidth-traffic and communication latency. The impacts of uniform and non-uniform distribution of cores into subnets on performance are also studied. VisualSim software package is used to model and simulate a traditional mesh and the proposed WNoC-CD and WNoC-DDs architectures by processing different communication scenarios. Experimental results show that the proposed WNoC-DDs reduces communication latency up to 20.54% and 5.40%, respectively, when compared to mesh and WNoC-CD. Similarly, the proposed WNoC-DDs reduces power consumption up to 73.56% and 19.97%, respectively, when compared to mesh and WNoC-CD. In a WNoC-DDs, each subnet works independently and resolves communication issues simultaneously. Experimental results also show that the non-uniform subnets help reduce communication latency up to 11.11% and reduces power consumption up to 14.76% when compared with the uniform subnets. Non-uniform partitioning provides flexibility of allocating tasks to different sized subnets as needed and thus improves the core utilization to a greater extent.
Book Synopsis Sustainable Wireless Network-on-Chip Architectures by : Jacob Ashton Murray
Download or read book Sustainable Wireless Network-on-Chip Architectures written by Jacob Ashton Murray and published by . This book was released on 2014 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: The dissertation focuses on power and thermal management strategies to enhance NoC sustainability. As hundreds of cores are integrated in a single chip, designing effective packages for dissipating maximum heat is infeasible. Moreover, technology scaling is pushing the limits of affordable cooling, thereby requiring suitable design techniques to reduce peak temperatures. Thus, addressing thermal concerns at different design stages is critical to the success of future generation systems.
Book Synopsis Design Space Exploration for Wireless Network-on-Chip Architectures by : Paul William Wettin
Download or read book Design Space Exploration for Wireless Network-on-Chip Architectures written by Paul William Wettin and published by . This book was released on 2014 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: The Network-on-Chip (NoC) paradigm has emerged as a scalable interconnection infrastructure for modern massive multicore chips. However, with growing levels of integration, the traditional NoCs suffer from high latency and energy dissipation in on-chip data transfer due to conventional multi-hop metal/dielectric based interconnects. Three-dimensional integration, on-chip photonics, RF, and wireless links have been proposed as radical low-power and low-latency alternatives to the conventional planar wire-based designs. Wireless NoCs with Carbon Nanotube (CNT) or millimeter (mm)-wave metal antennas are shown to outperform traditional wire based NoCs significantly in achievable data rate and energy dissipation. However, such emerging and transformative technologies can be prone to high levels of failures due to various issues related to manufacturing challenges and integration. On the other hand, several naturally occurring complex networks such as colonies of microbes and the World Wide Web are known to be inherently robust against high rates of failures and harsh environments. This thesis advocates adoption of such complex network based architectures to design wireless NoCs. This thesis presents a detailed performance analysis of small-world network enabled wireless NoC architectures in terms of achievable bandwidth, energy dissipation, thermal profiles and fault tolerance. The wireless NoC outperforms traditional wireline mesh architecture in terms of all the above-mentioned performance metrics. It also minimizes the effect of wireless link failures on the performance of the NoC. Through cycle accurate simulations it is shown that the wireless NoC architectures inspired by natural complex networks perform better than their conventional wired counterparts even in the presence of a high degree of link failures.
Book Synopsis Dynamic Voltage and Frequency Scaling for Wireless Network-on-chip by : Pratheep Joe Siluvai Iruthayaraj
Download or read book Dynamic Voltage and Frequency Scaling for Wireless Network-on-chip written by Pratheep Joe Siluvai Iruthayaraj and published by . This book was released on 2015 with total page 100 pages. Available in PDF, EPUB and Kindle. Book excerpt: "Previously, research and design of Network-on-Chip (NoC) paradigms where mainly focused on improving the performance of the interconnection networks. With emerging wide range of low-power applications and energy constrained high-performance applications, it is highly desirable to have NoCs that are highly energy efficient without incurring performance penalty. In the design of high-performance massive multi-core chips, power and heat have become dominant constrains. Increased power consumption can raise chip temperature, which in turn can decrease chip reliability and performance and increase cooling costs. It was proven that Small-world Wireless Network-on-Chip (SWNoC) architecture which replaces multi-hop wire-line path in a NoC by high-bandwidth single hop long range wireless links, reduces the overall energy dissipation when compared to wire-line mesh-based NoC architecture. However, the overall energy dissipation of the wireless NoC is still dominated by wire-line links and switches (buffers). Dynamic Voltage Scaling is an efficient technique for significant power savings in microprocessors. It has been proposed and deployed in modern microprocessors by exploiting the variance in processor utilization. On a Network-on-Chip paradigm, it is more likely that the wire-line links and buffers are not always fully utilized even for different applications. Hence, by exploiting these characteristics of the links and buffers over different traffic, DVFS technique can be incorporated on these switches and wire-line links for huge power savings. In this thesis, a history based DVFS mechanism is proposed. This mechanism uses the past utilization of the wire-line links & buffers to predict the future traffic and accordingly tune the voltage and frequency for the links and buffers dynamically for each time window. This mechanism dynamically minimizes the power consumption while substantially maintaining a high performance over the system. Performance analysis on these DVFS enabled Wireless NoC shows that, the overall energy dissipation is improved by around 40% when compared Small-world Wireless NoCs."--Abstract.
Book Synopsis Combined Dynamic Thermal Management Exploiting Broadcast-capable Wireless Network-on-chip Architecture by : Niraj Vasudevan
Download or read book Combined Dynamic Thermal Management Exploiting Broadcast-capable Wireless Network-on-chip Architecture written by Niraj Vasudevan and published by . This book was released on 2016 with total page 94 pages. Available in PDF, EPUB and Kindle. Book excerpt: "With the continuous scaling of device dimensions, the number of cores on a single die is constantly increasing. This integration of hundreds of cores on a single die leads to high power dissipation and thermal issues in modern Integrated Circuits (ICs). This causes problems related to reliability, timing violations and lifetime of electronic devices. Dynamic Thermal Management (DTM) techniques have emerged as potential solutions that mitigate the increasing temperatures on a die. However, considering the scaling of system sizes and the adoption of the Network-on-Chip (NoC) paradigm to serve as the interconnection fabric exacerbates the problem as both cores and NoC elements contribute to the increased heat dissipation on the chip. Typically, DTM techniques can either be proactive or reactive. Proactive DTM techniques, where the system has the ability to predict the thermal profile of the chip ahead of time are more desirable than reactive DTM techniques where the system utilizes thermal sensors to determine the current temperature of the chip. Moreover, DTM techniques either address core or NoC level thermal issues separately. Hence, this thesis proposes a combined proactive DTM technique that integrates both core level and NoC level DTM techniques. The combined DTM mechanism includes a dynamic temperature-aware routing approach for the NoC level elements, and includes task reallocation heuristics for the core level elements. On-chip wireless interconnects recently envisioned to enable energy-efficient data exchange between cores in a multicore chip will be used to provide a broadcast-capable medium to efficiently distribute thermal control messages to trigger and manage the DTM. Combining the proactive DTM technique with on-chip wireless interconnects, the on-chip temperature is restricted within target temperatures without significantly affecting the performance of the NoC based interconnection fabric of the multicore chip."--Abstract.
Book Synopsis Design of Wireless Network-on-chip for Improving Communication Performance of Many-core System-on-chips by : Yi Wang
Download or read book Design of Wireless Network-on-chip for Improving Communication Performance of Many-core System-on-chips written by Yi Wang and published by . This book was released on 2010 with total page 266 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis Towards a Scalable and Reliable Wireless Network-on-chip by : Amlan Ganguly
Download or read book Towards a Scalable and Reliable Wireless Network-on-chip written by Amlan Ganguly and published by . This book was released on 2010 with total page 112 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis Evaluation of Temperature-performance Trade-offs in Wireless Network-on-chip Architectures by : Nishad Nerurkar
Download or read book Evaluation of Temperature-performance Trade-offs in Wireless Network-on-chip Architectures written by Nishad Nerurkar and published by . This book was released on 2013 with total page 144 pages. Available in PDF, EPUB and Kindle. Book excerpt: "Continued scaling of device geometries according to Moore's Law is enabling complete end-user systems on a single chip. Massive multicore processors are enablers for many information and communication technology (ICT) innovations spanning various domains, including healthcare, defense, and entertainment. In the design of high-performance massive multicore chips, power and heat are dominant constraints. Temperature hotspots witnessed in multicore systems exacerbate the problem of reliability in deep submicron technologies. Hence, there is a great need to explore holistic power and thermal optimization and management strategies for the massive multicore chips. High power consumption not only raises chip temperature and cooling cost, but also decreases chip reliability and performance. thus, addressing thermal concerns at different stages of the design and operation is critical to the success of future generation systems. The performance of a multicore chip is also influenced by its overall communication infrastructure, which is predominantly a Network-on-Chip (NoC). The existing method of implementing a NoC with planar metal interconnects is deficient due to high latency, significant power consumption, and temperature hotspots arising out of long, multi-hop wireline links used in data exchange. On-chip wireless networks are envisioned as an enabling technology to design low power and high bandwidth massive multicore architectures. However, optimizing wireless NoCs for best performance does not necessarily guarantee a thermally optimal interconnection architecture. The wireless links being highly efficient attract very high traffic densities which in turn results in temperature hotspots. Therefore, while the wireless links result in better performance and energy-efficiency, they can also cause temperature hotspots and undermine the reliability of the system. Consequently, the location and utilization of the wireless links is an important factor in thermal optimization of high performance wireless Networks-on-Chip. Architectural innovation in conjunction with suitable power and thermal management strategies is the key for designing high performance yet energy-efficient massive multicore chips. This work contributes to exploration of various design methodologies for establishing wireless NoC architectures that achieve the best trade-offs between temperature, performance and energy-efficiency. It further demonstrates that incorporating Dynamic Thermal Management (DTM) on a multicore chip designed with such temperature and performance optimized Wireless Network-on-Chip architectures improves thermal profile while simultaneously providing lower latency and reduced network energy dissipation compared to its conventional counterparts."--Abstract.
Book Synopsis Broadcast-oriented Wireless Network-on-chip : Fundamentals and Feasibility by : Sergi Abadal Cavallé
Download or read book Broadcast-oriented Wireless Network-on-chip : Fundamentals and Feasibility written by Sergi Abadal Cavallé and published by . This book was released on 2016 with total page 200 pages. Available in PDF, EPUB and Kindle. Book excerpt: Recent years have seen the emergence and ubiquitous adoption of Chip Multiprocessors (CMPs), which rely on the coordinated operation of multiple execution units or cores. Successive CMP generations integrate a larger number of cores seeking higher performance with a reasonable cost envelope. For this trend to continue, however, important scalability issues need to be solved at different levels of design. Scaling the interconnect fabric is a grand challenge by itself, as new Network-on-Chip (NoC) proposals need to overcome the performance hurdles found when dealing with the increasingly variable and heterogeneous communication demands of manycore processors. Fast and flexible NoC solutions are needed to prevent communication become a performance bottleneck, situation that would severely limit the design space at the architectural level and eventually lead to the use of software frameworks that are slow, inefficient, or less programmable. The emergence of novel interconnect technologies has opened the door to a plethora of new NoCs promising greater scalability and architectural flexibility. In particular, wireless on-chip communication has garnered considerable attention due to its inherent broadcast capabilities, low latency, and system-level simplicity. Most of the resulting Wireless Network-on-Chip (WNoC) proposals have set the focus on leveraging the latency advantage of this paradigm by creating multiple wireless channels to interconnect far-apart cores. This strategy is effective as the complement of wired NoCs at moderate scales, but is likely to be overshadowed at larger scales by technologies such as nanophotonics unless bandwidth is unrealistically improved. This dissertation presents the concept of Broadcast-Oriented Wireless Network-on-Chip (BoWNoC), a new approach that attempts to foster the inherent simplicity, flexibility, and broadcast capabilities of the wireless technology by integrating one on-chip antenna and transceiver per processor core. This paradigm is part of a broader hybrid vision where the BoWNoC serves latency-critical and broadcast traffic, tightly coupled to a wired plane oriented to large flows of data. By virtue of its scalable broadcast support, BoWNoC may become the key enabler of a wealth of unconventional hardware architectures and algorithmic approaches, eventually leading to a significant improvement of the performance, energy efficiency, scalability and programmability of manycore chips. The present work aims not only to lay the fundamentals of the BoWNoC paradigm, but also to demonstrate its viability from the electronic implementation, network design, and multiprocessor architecture perspectives. An exploration at the physical level of design validates the feasibility of the approach at millimeter-wave bands in the short term, and then suggests the use of graphene-based antennas in the terahertz band in the long term. At the link level, this thesis provides an insightful context analysis that is used, afterwards, to drive the design of a lightweight protocol that reliably serves broadcast traffic with substantial latency improvements over state-of-the-art NoCs. At the network level, our hybrid vision is evaluated putting emphasis on the flexibility provided at the network interface level, showing outstanding speedups for a wide set of traffic patterns. At the architecture level, the potential impact of the BoWNoC paradigm on the design of manycore chips is not only qualitatively discussed in general, but also quantitatively assessed in a particular architecture for fast synchronization. Results demonstrate that the impact of BoWNoC can go beyond simply improving the network performance, thereby representing a possible game changer in the manycore era.
Book Synopsis Performance Evaluation and Design Trade-offs for Wireless Networks on Chip by : Kevin Chang
Download or read book Performance Evaluation and Design Trade-offs for Wireless Networks on Chip written by Kevin Chang and published by . This book was released on 2012 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: Massive levels of integration are making modern multi-core chips all pervasive in several domains. High performance, robustness, and energy-efficiency are crucial for the widespread adoption of such platforms. Networks-on-Chip (NoCs) have emerged as communication backbones to enable a high degree of integration in multi-core Systems-on-Chip (SoCs). Despite their advantages, an important performance limitation in traditional NoCs arises from planar metal interconnect-based multi-hop links with high latency and power consumption. This limitation can be addressed by drawing inspiration from the evolution of natural complex networks, which offer great performance-cost trade-offs. Analogous with many natural complex systems, future multi-core chips are expected to be hierarchical and heterogeneous in nature as well. In this paper we undertake a detailed performance evaluation for hierarchical small-world NoC architectures where the long-range communications links are established through the millimeter-wave wireless communication channels. Through architecture-space exploration in conjunction with novel power efficient on-chip wireless link design, we demonstrate that it is possible to improve performance of conventional NoC architectures significantly without incurring high area overhead.
Book Synopsis Adaptive Code Division Multiple Access Protocol for Wireless Network-on-chip Architectures by : Vineeth Vijayakumaran
Download or read book Adaptive Code Division Multiple Access Protocol for Wireless Network-on-chip Architectures written by Vineeth Vijayakumaran and published by . This book was released on 2012 with total page 120 pages. Available in PDF, EPUB and Kindle. Book excerpt: "Massive levels of integration following Moore's Law ushered in a paradigm shift in the way on-chip interconnections were designed. With higher and higher number of cores on the same die traditional bus based interconnections are no longer a scalable communication infrastructure. On-chip networks were proposed enabled a scalable plug-and-play mechanism for interconnecting hundreds of cores on the same chip. Wired interconnects between the cores in a traditional Network-on-Chip (NoC) system, becomes a bottleneck with increase in the number of cores thereby increasing the latency and energy to transmit signals over them. Hence, there has been many alternative emerging interconnect technologies proposed, namely, 3D, photonic and multi-band RF interconnects. Although they provide better connectivity, higher speed and higher bandwidth compared to wired interconnects; they also face challenges with heat dissipation and manufacturing difficulties. On-chip wireless interconnects is one other alternative proposed which doesn't need physical interconnection layout as data travels over the wireless medium. They are integrated into a hybrid NOC architecture consisting of both wired and wireless links, which provides higher bandwidth, lower latency, lesser area overhead and reduced energy dissipation in communication. However, as the bandwidth of the wireless channels is limited, an efficient media access control (MAC) scheme is required to enhance the utilization of the available bandwidth. This thesis proposes using a multiple access mechanism such as Code Division Multiple Access (CDMA) to enable multiple transmitter-receiver pairs to send data over the wireless channel simultaneously. It will be shown that such a hybrid wireless NoC with an efficient CDMA based MAC protocol can significantly increase the performance of the system while lowering the energy dissipation in data transfer. In this work it is shown that the wireless NoC with the proposed CDMA based MAC protocol outperformed the wired counterparts and several other wireless architectures proposed in literature in terms of bandwidth and packet energy dissipation. Significant gains were observed in packet energy dissipation and bandwidth even with scaling the system to higher number of cores. Non-uniform traffic simulations showed that the proposed CDMA-WiNoC was consistent in bandwidth across all traffic patterns. It is also shown that the CDMA based MAC scheme does not introduce additional reliability concerns in data transfer over the on-chip wireless interconnects."--Abstract.
Book Synopsis Design Trade-offs for Reliable On-chip Wireless Interconnects in NoC Platforms by : Manoj Prashanth Yuvaraj
Download or read book Design Trade-offs for Reliable On-chip Wireless Interconnects in NoC Platforms written by Manoj Prashanth Yuvaraj and published by . This book was released on 2014 with total page 146 pages. Available in PDF, EPUB and Kindle. Book excerpt: "The massive levels of integration following Moore's Law making modern multi-core chips prevail in various domains ranging from scientific applications to bioinformatics applications for consumer electronics. With higher and higher number of cores on the same die traditional bus based interconnections are no longer a scalable communication infrastructure. On-chip networks were proposed enabled a scalable plug-and-play mechanism for interconnecting hundreds of cores on the same chip. Wired interconnects between the cores in a traditional Network-on-Chip (NoC) system, becomes a bottleneck with increase in the number of cores thereby increasing the latency and energy to transmit signals over them. Hence, there has been many alternative emerging interconnect technologies proposed, namely, 3D, photonic and multi-band RF interconnects. Although they provide better connectivity, higher speed and higher bandwidth compared to wired interconnects; they also face challenges with heat dissipation and manufacturing difficulties. On-chip wireless interconnects is one other alternative proposed which doesn't need physical interconnection layout as data travels over the wireless medium. They are integrated into a hybrid NOC architecture consisting of both wired and wireless links, which provides higher bandwidth, lower latency, lesser area overhead and reduced energy dissipation in communication. An efficient media access control (MAC) scheme is required to enhance the utilization of the available bandwidth. A token-passing protocol proposed to grant access of the wireless channel to competing transmitters. This limits the number of simultaneous users of the communication channel to one although multiple wireless hubs are deployed over the chip. In principle, a Frequency Division Multiple Access (FDMA) based medium access scheme would improve the utilization of the wireless resources. However, this requires design of multiple very precise, high frequency transceivers in non-overlapping frequency channels. Therefore, the scalability of this approach is limited by the state-of-the-art in transceiver design. The Code Division Multiple Access (CDMA) enables multiple transmitter-receiver pairs to send data over the wireless channel simultaneously. The CDMA protocol can significantly increase the performance of the system while lowering the energy dissipation in data transfer. The CDMA based MAC protocol outperforms the wired counterparts and several other wireless architectures proposed in literature in terms of bandwidth and packet energy dissipation. However, the reliability of CDMA based wireless NoC's is limited, as the probability of error is eminent due to synchronization delays at the receiver. The thesis proposes the use of an advanced filter which improves the performance and also reduces the error due to synchronization delays. This thesis also proposes investigation of various channel modulation schemes on token passing wireless NoC's to examine the performance and reliability of the system. The trade-off between performance and energy are established for the various conditions. The results are obtained using a modified cycle accurate simulator."--Abstract.
Book Synopsis Architecting a One-to-many Traffic-aware and Secure Millimeter-wave Wireless Network-in-package Interconnect for Multichip Systems by : M. Meraj Ahmed
Download or read book Architecting a One-to-many Traffic-aware and Secure Millimeter-wave Wireless Network-in-package Interconnect for Multichip Systems written by M. Meraj Ahmed and published by . This book was released on 2021 with total page 166 pages. Available in PDF, EPUB and Kindle. Book excerpt: "With the aggressive scaling of device geometries, the yield of complex Multi Core Single Chip(MCSC) systems with many cores will decrease due to the higher probability of manufacturing defects especially, in dies with a large area. Disintegration of large System-on-Chips(SoCs) into smaller chips called chiplets has shown to improve the yield and cost of complex systems. Therefore, platform-based computing modules such as embedded systems and micro-servers have already adopted Multi Core Multi Chip (MCMC) architectures over MCSC architectures. Due to the scaling of memory intensive parallel applications in such systems, data is more likely to be shared among various cores residing in different chips resulting in a significant increase in chip-to-chip traffic, especially one-to-many traffic. This one-to-many traffic is originated mainly to maintain cache-coherence between many cores residing in multiple chips. Besides, one-to-many traffics are also exploited by many parallel programming models, system-level synchronization mechanisms, and control signals. How-ever, state-of-the-art Network-on-Chip (NoC)-based wired interconnection architectures do not provide enough support as they handle such one-to-many traffic as multiple unicast trafficusing a multi-hop MCMC communication fabric. As a result, even a small portion of such one-to-many traffic can significantly reduce system performance as traditional NoC-basedinterconnect cannot mask the high latency and energy consumption caused by chip-to-chipwired I/Os. Moreover, with the increase in memory intensive applications and scaling of MCMC systems, traditional NoC-based wired interconnects fail to provide a scalable inter-connection solution required to support the increased cache-coherence and synchronization generated one-to-many traffic in future MCMC-based High-Performance Computing (HPC) nodes. Therefore, these computation and memory intensive MCMC systems need an energy-efficient, low latency, and scalable one-to-many (broadcast/multicast) traffic-aware interconnection infrastructure to ensure high-performance. Research in recent years has shown that Wireless Network-in-Package (WiNiP) architectures with CMOS compatible Millimeter-Wave (mm-wave) transceivers can provide a scalable, low latency, and energy-efficient interconnect solution for on and off-chip communication. In this dissertation, a one-to-many traffic-aware WiNiP interconnection architecture with a starvation-free hybrid Medium Access Control (MAC), an asymmetric topology, and a novel flow control has been proposed. The different components of the proposed architecture are individually one-to-many traffic-aware and as a system, they collaborate with each other to provide required support for one-to-many traffic communication in a MCMC environment. It has been shown that such interconnection architecture can reduce energy consumption and average packet latency by 46.96% and 47.08% respectively for MCMC systems. Despite providing performance enhancements, wireless channel, being an unguided medium, is vulnerable to various security attacks such as jamming induced Denial-of-Service (DoS), eavesdropping, and spoofing. Further, to minimize the time-to-market and design costs, modern SoCs often use Third Party IPs (3PIPs) from untrusted organizations. An adversary either at the foundry or at the 3PIP design house can introduce a malicious circuitry, to jeopardize an SoC. Such malicious circuitry is known as a Hardware Trojan (HT). An HTplanted in the WiNiP from a vulnerable design or manufacturing process can compromise a Wireless Interface (WI) to enable illegitimate transmission through the infected WI resulting in a potential DoS attack for other WIs in the MCMC system. Moreover, HTs can be used for various other malicious purposes, including battery exhaustion, functionality subversion, and information leakage. This information when leaked to a malicious external attackercan reveals important information regarding the application suites running on the system, thereby compromising the user profile. To address persistent jamming-based DoS attack in WiNiP, in this dissertation, a secure WiNiP interconnection architecture for MCMC systems has been proposed that re-uses the one-to-many traffic-aware MAC and existing Design for Testability (DFT) hardware along with Machine Learning (ML) approach. Furthermore, a novel Simulated Annealing (SA)-based routing obfuscation mechanism was also proposed toprotect against an HT-assisted novel traffic analysis attack. Simulation results show that,the ML classifiers can achieve an accuracy of 99.87% for DoS attack detection while SA-basedrouting obfuscation could reduce application detection accuracy to only 15% for HT-assistedtraffic analysis attack and hence, secure the WiNiP fabric from age-old and emerging attacks."--Abstract.
Book Synopsis An Interconnection Architecture for Seamless Inter and Intra-chip Communication Using Wireless Links by : Jagan Muralidharan
Download or read book An Interconnection Architecture for Seamless Inter and Intra-chip Communication Using Wireless Links written by Jagan Muralidharan and published by . This book was released on 2015 with total page 84 pages. Available in PDF, EPUB and Kindle. Book excerpt: "As semiconductor technologies continues to scale, more and more cores are being integrated on the same multicore chip. This increase in complexity poses the challenge of efficient data transfer between these cores. Several on-chip network architectures are proposed to improve the design flexibility and communication efficiency of such multicore chips. However, in a larger system consisting of several multicore chips across a board or in a System-in-Package (SiP), the performance is limited by the communication among and within these chips. Such systems, most commonly found within computing modules in typical data center nodes or server racks, are in dire need of an efficient interconnection architecture. Conventional interchip communication using wireline links involve routing the data from the internal cores to the peripheral I/O ports, travelling over the interchip channels to the destination chip, and finally getting routed from the I/O to the internal cores there. This multihop communication increases latency and energy consumption while decreasing data bandwidth in a multichip system. Furthermore, the intrachip and interchip communication architectures are separately designed to maximize design flexibility. Jointly designing them could, however, improve the communication efficiency significantly and yield better solutions. Previous attempts at this include an all-photonic approach that provides a unified inter/intra-chip optical network, based on recent progress in nano-photonic technologies. Works on wireless inter-chip interconnects successfully yielded better results than their wired counterparts, but their scopes were limited to establishing a single wireless connection between two chips rather than a communication architecture for a system as a whole. In this thesis, the design of a seamless hybrid wired and wireless interconnection network for multichip systems in a package is proposed. The design utilizes on-chip wireless transceivers with dimensions spanning up to tens of centimeters. It manages to seamlessly bind both intrachip and interchip communication architectures and enables direct chip-to-chip communication between the internal cores. It is shown through cycle accurate simulations that the proposed design increases the bandwidth and reduces the energy consumption when compared to the state-of-the-art wireline I/O based multichip communications."--Abstract.
Book Synopsis Design and Application of Advanced Network-on-chip Architecture by : Wen-Hsiang Hu
Download or read book Design and Application of Advanced Network-on-chip Architecture written by Wen-Hsiang Hu and published by . This book was released on 2011 with total page 127 pages. Available in PDF, EPUB and Kindle. Book excerpt: As semiconductor technology continues its phenomenal growth and follows the Moore's Law, the amount of computation power and storage that can be integrated on a chip increases. However, the performance of on-chip interconnections does not scale as well. Interconnects are increasingly becoming the bottleneck limiting performance, cost, and power in all types of systems. Traditional bus architecture no longer can fulfill the stringent application requirements. Network-on-chip (NoC) architecture is proposed as a unified solution for the design problems faced in advanced process technology. In order for NoC technologies to be successful, careful attention should be paid to every aspect of NoC design, including topology, flow control, routing algorithm, router architecture, and programming. This dissertation proposes two advanced NoC architectures based on imminent fabrication technologies. The first one deploys diagonal channels together with a quasi-minimal adaptive routing algorithm for a two-dimensional mesh network. The design and implementation of the router architecture is also realized in Verilog to perform analysis of area cost and power consumption. Experimental results show that not only transfer latency and throughput are greatly improved, power dissipation is also decreased by the use of diagonal links. Furthermore, a low-cost congestion-aware routing algorithm is devised to resolve imbalance in link load and enhance saturation load. To overcome long transmission latency and high power consumption due to multi-hop communications in NoC, applying on-chip wireless communication is also investigated. A hybrid on-chip communication infrastructure which incorporates on-chip wireless interconnect with existing wired NoC is developed. Wireless links are inserted between clusters of routers to form express communication links. Simulated annealing optimization techniques are employed to find optimal locations for wireless routers so communication latency was minimized. Virtual channel flow control is utilized to prevent deadlock introduced by the hybrid architecture. Performance and feasibility analysis demonstrates the benefits of our approach over the wired counterpart. This dissertation also addresses some of key programming challenges in NoC architecture. The decoding algorithm of Low Density Parity Check (LDPC) codes is used as a case study for this purpose. A parallelization scheme for LDPC decoding is devised for a NoC-based multiprocessor platform. Issues on partitioning, mapping and scheduling of LDPC decoding on such a platform will be discussed. As a result, the memory bottleneck, commonly seen in LDPC decoder design, is eliminated by the proposed approach. A graph spectra based mapping algorithm is developed to minimize heavy message exchanges among processors during the decoding process. Experimental results from various LDPC codes demonstrate that desirable scalability and speedups are obtained.
Book Synopsis Sustainable Wireless Network-on-Chip Architectures by : Jacob Murray
Download or read book Sustainable Wireless Network-on-Chip Architectures written by Jacob Murray and published by Morgan Kaufmann. This book was released on 2016-03-25 with total page 163 pages. Available in PDF, EPUB and Kindle. Book excerpt: Sustainable Wireless Network-on-Chip Architectures focuses on developing novel Dynamic Thermal Management (DTM) and Dynamic Voltage and Frequency Scaling (DVFS) algorithms that exploit the advantages inherent in WiNoC architectures. The methodologies proposed—combined with extensive experimental validation—collectively represent efforts to create a sustainable NoC architecture for future many-core chips. Current research trends show a necessary paradigm shift towards green and sustainable computing. As implementing massively parallel energy-efficient CPUs and reducing resource consumption become standard, and their speed and power continuously increase, energy issues become a significant concern. The need for promoting research in sustainable computing is imperative. As hundreds of cores are integrated in a single chip, designing effective packages for dissipating maximum heat is infeasible. Moreover, technology scaling is pushing the limits of affordable cooling, thereby requiring suitable design techniques to reduce peak temperatures. Addressing thermal concerns at different design stages is critical to the success of future generation systems. DTM and DVFS appear as solutions to avoid high spatial and temporal temperature variations among NoC components, and thereby mitigate local network hotspots. Defines new complex, sustainable network-on-chip architectures to reduce network latency and energy Develops topology-agnostic dynamic thermal management and dynamic voltage and frequency scaling techniques Describes joint strategies for network- and core-level sustainability Discusses novel algorithms that exploit the advantages inherent in Wireless Network-on-Chip architectures
Author :Chrysostomos Nicopoulos Publisher :Springer Science & Business Media ISBN 13 :904813031X Total Pages :237 pages Book Rating :4.0/5 (481 download)
Book Synopsis Network-on-Chip Architectures by : Chrysostomos Nicopoulos
Download or read book Network-on-Chip Architectures written by Chrysostomos Nicopoulos and published by Springer Science & Business Media. This book was released on 2009-09-18 with total page 237 pages. Available in PDF, EPUB and Kindle. Book excerpt: [2]. The Cell Processor from Sony, Toshiba and IBM (STI) [3], and the Sun UltraSPARC T1 (formerly codenamed Niagara) [4] signal the growing popularity of such systems. Furthermore, Intel’s very recently announced 80-core TeraFLOP chip [5] exemplifies the irreversible march toward many-core systems with tens or even hundreds of processing elements. 1.2 The Dawn of the Communication-Centric Revolution The multi-core thrust has ushered the gradual displacement of the computati- centric design model by a more communication-centric approach [6]. The large, sophisticated monolithic modules are giving way to several smaller, simpler p- cessing elements working in tandem. This trend has led to a surge in the popularity of multi-core systems, which typically manifest themselves in two distinct incarnations: heterogeneous Multi-Processor Systems-on-Chip (MPSoC) and homogeneous Chip Multi-Processors (CMP). The SoC philosophy revolves around the technique of Platform-Based Design (PBD) [7], which advocates the reuse of Intellectual Property (IP) cores in flexible design templates that can be customized accordingly to satisfy the demands of particular implementations. The appeal of such a modular approach lies in the substantially reduced Time-To- Market (TTM) incubation period, which is a direct outcome of lower circuit complexity and reduced design effort. The whole system can now be viewed as a diverse collection of pre-existing IP components integrated on a single die.
