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Design Techniques For Low Power High Speed Successive Approximation Analog To Digital Converters
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Book Synopsis Design Techniques for Low Power High Speed Successive Approximation Analog-to-digital Converters by : Jiaming Lin
Download or read book Design Techniques for Low Power High Speed Successive Approximation Analog-to-digital Converters written by Jiaming Lin and published by . This book was released on 2013 with total page 75 pages. Available in PDF, EPUB and Kindle. Book excerpt: This dissertation presents two high-speed pipeline successive approximation analog-to-digital converters (SAR ADCs). Capacitive DACs and resistive DACs are utilized in these two pipeline SAR ADCs, respectively. The pipeline SAR ADC with capacitive DACs can save 50% switching power compared with other time-interleaved SAR ADCs since the total capacitance of the DACs in this ADC is more than 50% less than the conventional time-interleave ones. Several switching techniques are implemented to alleviate the impact from the parasitic capacitance and improve the performance. The pipeline SAR ADC with resistive DACs overcomes the influence from the parasitic capacitance with negligible static power consumption on the resistive DACs. Also, the complicated switching techniques can be avoided to simplify the timing logic. To verify the above two architectures, two chips were designed and fabricated in 40nm CMOS process. Finally, a new architecture of multi-step capacitive-splitting SAR ADC is proposed for low power applications. By using two identical capacitor-splitting capacitor arrays, the switching power and capacitor area can be reduced significantly.
Book Synopsis Low-power Techniques for Successive Approximation Register (SAR) Analog-to-digital Converters by : Ramgopal Sekar
Download or read book Low-power Techniques for Successive Approximation Register (SAR) Analog-to-digital Converters written by Ramgopal Sekar and published by . This book was released on 2010 with total page 160 pages. Available in PDF, EPUB and Kindle. Book excerpt: In this work, the author investigated circuit techniques to reduce the power consumption of Successive Approximation Register Analog-to-Digital Converter (SAR-ADC). The author developed four low-power SAR-ADC design techniques, which are: (1) Low-power SAR-ADC design with split voltage reference, (2) Charge recycling techniques for low-power SAR-ADC design, (3) Low-power SAR-ADC design using two-capacitor arrays, (4) Power reduction techniques by dynamically minimizing SAR-ADC conversion cycles. Matlab simulations are performed to investigate the power saving by the proposed techniques. Simulation results show that significant power reduction can be achieved by using the developed techniques. In addition, design issues such as area overhead, design complexity associated with the proposed low-power techniques are also discussed in the thesis.
Book Synopsis Low-Power High-Resolution Analog to Digital Converters by : Amir Zjajo
Download or read book Low-Power High-Resolution Analog to Digital Converters written by Amir Zjajo and published by Springer Science & Business Media. This book was released on 2010-10-29 with total page 311 pages. Available in PDF, EPUB and Kindle. Book excerpt: With the fast advancement of CMOS fabrication technology, more and more signal-processing functions are implemented in the digital domain for a lower cost, lower power consumption, higher yield, and higher re-configurability. This has recently generated a great demand for low-power, low-voltage A/D converters that can be realized in a mainstream deep-submicron CMOS technology. However, the discrepancies between lithography wavelengths and circuit feature sizes are increasing. Lower power supply voltages significantly reduce noise margins and increase variations in process, device and design parameters. Consequently, it is steadily more difficult to control the fabrication process precisely enough to maintain uniformity. The inherent randomness of materials used in fabrication at nanoscopic scales means that performance will be increasingly variable, not only from die-to-die but also within each individual die. Parametric variability will be compounded by degradation in nanoscale integrated circuits resulting in instability of parameters over time, eventually leading to the development of faults. Process variation cannot be solved by improving manufacturing tolerances; variability must be reduced by new device technology or managed by design in order for scaling to continue. Similarly, within-die performance variation also imposes new challenges for test methods. In an attempt to address these issues, Low-Power High-Resolution Analog-to-Digital Converters specifically focus on: i) improving the power efficiency for the high-speed, and low spurious spectral A/D conversion performance by exploring the potential of low-voltage analog design and calibration techniques, respectively, and ii) development of circuit techniques and algorithms to enhance testing and debugging potential to detect errors dynamically, to isolate and confine faults, and to recover errors continuously. The feasibility of the described methods has been verified by measurements from the silicon prototypes fabricated in standard 180nm, 90nm and 65nm CMOS technology.
Book Synopsis Time-interleaved Analog-to-Digital Converters by : Simon Louwsma
Download or read book Time-interleaved Analog-to-Digital Converters written by Simon Louwsma and published by Springer Science & Business Media. This book was released on 2010-09-08 with total page 148 pages. Available in PDF, EPUB and Kindle. Book excerpt: Time-interleaved Analog-to-Digital Converters describes the research performed on low-power time-interleaved ADCs. A detailed theoretical analysis is made of the time-interleaved Track & Hold, since it must be capable of handling signals in the GHz range with little distortion, and minimal power consumption. Timing calibration is not attractive, therefore design techniques are presented which do not require timing calibration. The design of power efficient sub-ADCs is addressed with a theoretical analysis of a successive approximation converter and a pipeline converter. It turns out that the first can consume about 10 times less power than the latter, and this conclusion is supported by literature. Time-interleaved Analog-to-Digital Converters describes the design of a high performance time-interleaved ADC, with much attention for practical design aspects, aiming at both industry and research. Measurements show best-inclass performance with a sample-rate of 1.8 GS/s, 7.9 ENOBs and a power efficiency of 1 pJ/conversion-step.
Book Synopsis Offset Reduction Techniques in High-Speed Analog-to-Digital Converters by : Pedro M. Figueiredo
Download or read book Offset Reduction Techniques in High-Speed Analog-to-Digital Converters written by Pedro M. Figueiredo and published by Springer Science & Business Media. This book was released on 2009-03-10 with total page 395 pages. Available in PDF, EPUB and Kindle. Book excerpt: Offset Reduction Techniques in High-Speed Analog-to-Digital Converters analyzes, describes the design, and presents test results of Analog-to-Digital Converters (ADCs) employing the three main high-speed architectures: flash, two-step flash and folding and interpolation. The advantages and limitations of each one are reviewed, and the techniques employed to improve their performance are discussed.
Book Synopsis Generalized Low-Voltage Circuit Techniques for Very High-Speed Time-Interleaved Analog-to-Digital Converters by : Sai-Weng Sin
Download or read book Generalized Low-Voltage Circuit Techniques for Very High-Speed Time-Interleaved Analog-to-Digital Converters written by Sai-Weng Sin and published by Springer Science & Business Media. This book was released on 2010-09-29 with total page 147 pages. Available in PDF, EPUB and Kindle. Book excerpt: Analog-to-Digital Converters (ADCs) play an important role in most modern signal processing and wireless communication systems where extensive signal manipulation is necessary to be performed by complicated digital signal processing (DSP) circuitry. This trend also creates the possibility of fabricating all functional blocks of a system in a single chip (System On Chip - SoC), with great reductions in cost, chip area and power consumption. However, this tendency places an increasing challenge, in terms of speed, resolution, power consumption, and noise performance, in the design of the front-end ADC which is usually the bottleneck of the whole system, especially under the unavoidable low supply-voltage imposed by technology scaling, as well as the requirement of battery operated portable devices. Generalized Low-Voltage Circuit Techniques for Very High-Speed Time-Interleaved Analog-to-Digital Converters will present new techniques tailored for low-voltage and high-speed Switched-Capacitor (SC) ADC with various design-specific considerations.
Book Synopsis Accelerated Successive Approximation Technique for Analog to Digital Converter Design by : Ram Harshvardhan Radhakrishnan
Download or read book Accelerated Successive Approximation Technique for Analog to Digital Converter Design written by Ram Harshvardhan Radhakrishnan and published by . This book was released on 2015 with total page 82 pages. Available in PDF, EPUB and Kindle. Book excerpt: This thesis work presents a novel technique to reduce the number of conversion cycles for Successive Approximation register (SAR) Analog to Digital Converters (ADC), thereby potentially improving the conversion speed as well as reducing its power consumption. Conventional SAR ADCs employ the binary search algorithm and they update only one bound, either the upper or lower bound, of the search space during one conversion cycle. The proposed method, referred to as the Accelerated-SAR or A-SAR, is capable of updating both the lower and upper bounds in a single conversion cycle. Even in cases that it can update only one bound, it does more aggressively. The proposed technique is implemented in a 10-bit SAR ADC circuit with 0.5V power supply and rail-to-rail input range. To cope with the ultra-low voltage design challenge, Time-to-Digital conversion techniques are used in the implementation. Important design issues are also discussed for the charge scaling array and Voltage Controlled Delay Lines (VCDL), which are important building blocks in the ADC implementation.
Book Synopsis Design of High-Speed Energy-Efficient Successive-Approximation Analog-to-Digital Converters by : 劉純成
Download or read book Design of High-Speed Energy-Efficient Successive-Approximation Analog-to-Digital Converters written by 劉純成 and published by . This book was released on 2010 with total page 182 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis Digitally Assisted Techniques for Nyquist Rate Analog-to-Digital Converters by : Rabeeh Majidi
Download or read book Digitally Assisted Techniques for Nyquist Rate Analog-to-Digital Converters written by Rabeeh Majidi and published by . This book was released on 2015 with total page 204 pages. Available in PDF, EPUB and Kindle. Book excerpt: Abstract: With the advance of technology and rapid growth of digital systems, low power high speed analog-to- digital converters with great accuracy are in demand. To achieve high effective number of bits Analog-to-Digital Converter (ADC) calibration as a time consuming process is a potential bottleneck for designs. This dissertation presentsa fully digital background calibration algorithm for a 7- bit redundant flash ADC using split structure and look-up table based correction. Redundant comparators are used in the flash ADC design of this work in order to tolerate large offset voltages while minimizing signal input capacitance. The split ADC structure helps by eliminating the unknown input signal from the calibration path. The flash ADC has been designed in 180nm IBM CMOS technology and fabricated through MOSIS. This work was supported by Analog Devices, Wilmington, MA. While much research on ADC design has concentrated on increasing resolution and sample rate, there are many applications (e.g. biomedical devices and sensor networks) that do not require high performance but do require low power energy efficient ADCs. This dissertation also explores on design of a low quiescent current 100k Sps Successive Approximation (SAR) ADC that has been used as an error detection ADC for an automotive application in 350nm CD (CMOS-DMOS) technology. This work was supported by ON Semiconductor Corp, East Greenwich, RI.
Book Synopsis Design Techniques for Ultra-High-Speed Time-Interleaved Analog-to-Digital Converters by : Yida Duan
Download or read book Design Techniques for Ultra-High-Speed Time-Interleaved Analog-to-Digital Converters written by Yida Duan and published by . This book was released on 2015 with total page 80 pages. Available in PDF, EPUB and Kindle. Book excerpt: Analog-to-Digital Converters (ADCs) serve as the interfaces between the analog natural world and the binary world of computer data. Due to this essential role, ADC circuits have been well studied over 40 years, and many problems associated with them have already been solved. However in recent years, a new species of ADCs has appeared, and since then attracted lots of attention. These are ultra-high-speed (often greater than 40GS/s) time-interleaved ADCs of low or medium resolution (around 6 to 8 bit) built in CMOS processes. Although such ADCs can be used in high-speed electronic measurement equipment and radar systems, the recent driving force behind them is next generation 100Gbps/400Gbps fiber optical transceivers. These transceivers take advantage of ultra-high-speed ADCs and digital-signal-processors (DSPs) to enable ultra-high data-rate communications in long-haul networks (city-to-city, transcontinental, and transoceanic fiber links), metro networks (fibers that connect enterprises in metropolitan areas), and data centers (fiber links within data center infrastructures). At such high sampling rate, massively time-interleaved successive-approximation ADC (SAR ADC) architecture has emerged as the dominant solution due to its excellent power efficiency. Several recent works has demonstrated success in achieving high sampling rate. However, the sampling network has become the bottleneck that limits the input bandwidth in these ADCs. It is apparent that conventional switch-based track-and-hold (T&H) circuit cannot satisfy the >20GHz bandwidth requirement. In addition, it is unclear what the optimal interleaving configuration is. Each state-of-the-art design adopts a different interleaving configuration - from straightforward conventional 1-rank interleaving to 2-rank hierarchical sampling or even 3 ranks. How to partition interleaving factors among different ranks has not yet been investigated. Furthermore, asynchronous SAR sub-ADCs are often used in these designs to push the sampling rate even further. The well-known sparkle-code issues caused by comparator meta-stability in asynchronous SARs can significantly increase the Bit-Error-Rate (BER) of the transceivers unless power hungry error correction coding are implemented in the system. Although many works in the literature attempted to deal with the meta-stability in asynchronous SARs, the effectiveness of these approaches have not been fully demonstrated. In this thesis, I will first propose a new cascode-based T&H circuits to improve the ADC bandwidth beyond the limit of conventional switch-based T&H circuits. Then, a system design and optimization methodology of hierarchical time-interleaved sampling network is presented in the context of cascode T&H. To deal with sparkle-code issue in asynchronous SAR sub-ADCs, a new back-end meta-stability correction technique is employed. An extensive statistical analysis is provided to verify the correction algorithm can greatly reduce sparkle-code error-rates. To further demonstrate the effectiveness of the proposed circuits and techniques, two prototype ADCs have been implemented. The first 7b 12.5GS/s hierarchically time-interleaved ADC in 65nm CMOS process demonstrates 29.4dB SNDR and >25GHz bandwidth. The later 6b 46GS/s ADC in 28nm CMOS employs asynchronous SAR sub-ADC design with back-end meta-stability correction. The measurement results show it achieves sparkle-code error free operation over 1e10 samples in addition to achieving >23GHz bandwidth and 25.2dB SNDR. The power consumption is 381mW from 1.05V/1.6V supplies, and the FOM is 0.56pJ/conversion-step.
Book Synopsis Low Power High Performance Successive Approximation Analog to Digital Converter by : Rabeeh Majidi
Download or read book Low Power High Performance Successive Approximation Analog to Digital Converter written by Rabeeh Majidi and published by . This book was released on 2010 with total page 112 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis Design of High-speed Energy-efficient Successive-approximation Register Analog-to-digital Converters by : 張廷愷
Download or read book Design of High-speed Energy-efficient Successive-approximation Register Analog-to-digital Converters written by 張廷愷 and published by . This book was released on 2014 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis Data Conversion Handbook by : Walt Kester
Download or read book Data Conversion Handbook written by Walt Kester and published by Newnes. This book was released on 2005 with total page 977 pages. Available in PDF, EPUB and Kindle. Book excerpt: This complete update of a classic handbook originally created by Analog Devices and never previously published offers the most complete and up-to-date reference available on data conversion, from the world authority on the subject. It describes in depth the theory behind and the practical design of data conversion circuits. It describes the different architectures used in A/D and D/A converters - including many advances that have been made in this technology in recent years - and provides guidelines on which types are best suited for particular applications. It covers error characterization and testing specifications, essential design information that is difficult to find elsewhere. The book also contains a wealth of practical application circuits for interfacing and supporting A/D and D/A converters within an electronic system. In short, everything an electronics engineer needs to know about data converters can be found in this volume, making it an indispensable reference with broad appeal. The accompanying CD-ROM provides software tools for testing and analyzing data converters as well as a searchable pdf version of the text. * brings together a huge amount of information impossible to locate elsewhere. * many recent advances in converter technology simply aren't covered in any other book. * a must-have design reference for any electronics design engineer or technician
Book Synopsis Advances in Analog and RF IC Design for Wireless Communication Systems by : Kostas Doris
Download or read book Advances in Analog and RF IC Design for Wireless Communication Systems written by Kostas Doris and published by Elsevier Inc. Chapters. This book was released on 2013-05-13 with total page 41 pages. Available in PDF, EPUB and Kindle. Book excerpt: This paper reviews recent developments of interleaved Successive Approximation Analog-to-Digital converters (SAR) in deep sub-micron CMOS technologies. The discussion covers design tradeoffs and degrees of freedom related to the impact of extensive interleaving with many SAR units on bandwidth, noise, linearity, and spurious performance. The impact of interleaving mismatches on representative broadband and multi-carrier narrowband signals is also discussed. Next, two examples are given demonstrating how interleaving with many ADCs can be transformed from a weakness to a strength. The first example concerns low spurious performance enabled by redundant SAR converters and randomization of their operation. The second example presents spectral sensing techniques.
Book Synopsis High-Speed Analog-to-Digital Conversion by : Michael J. Demler
Download or read book High-Speed Analog-to-Digital Conversion written by Michael J. Demler and published by Elsevier. This book was released on 2012-12-02 with total page 233 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book covers the theory and applications of high-speed analog-to-digital conversion. An analog-to-digital converter takes real-world inputs (such as visual images, temperature readings, and rates of speed) and transforms them into digital form for processing by computer. This book discusses the design and uses of such circuits, with particular emphasis on improving the speed of the conversion process and the accuracy of its output--how well the output is a corresponding digital representation of the output*b1input signal. As computers become increasingly interfaced to the outside world, "ADC" techniques will become ever more important.
Book Synopsis Ultra-Low-Voltage Frequency Synthesizer and Successive-Approximation Analog-to-Digital Converter for Biomedical Applications by : Chung-Chih Hung
Download or read book Ultra-Low-Voltage Frequency Synthesizer and Successive-Approximation Analog-to-Digital Converter for Biomedical Applications written by Chung-Chih Hung and published by Springer Nature. This book was released on 2021-12-07 with total page 231 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book introduces the origin of biomedical signals and the operating principles behind them and introduces the characteristics of common biomedical signals for subsequent signal measurement and judgment. Since biomedical signals are captured by wearable devices, sensor devices, or implanted devices, these devices are all battery-powered to maintain long working time. We hope to reduce their power consumption to extend service life, especially for implantable devices, because battery replacement can only be done through surgery. Therefore, we must understand how to design low-power integrated circuits. Both implantable and in-vitro medical signal detectors require two basic components to collect and transmit biomedical signals: an analog-to-digital converter and a frequency synthesizer because these measured biomedical signals are wirelessly transmitted to the relevant receiving unit. The core unit of wireless transmission is the frequency synthesizer, which provides a wide frequency range and stable frequency to demonstrate the quality and performance of the wireless transmitter. Therefore, the basic operating principle and model of the frequency synthesizer are introduced. We also show design examples and measurement results of a low-power low-voltage integer-N frequency synthesizer for biomedical applications. The detection of biomedical signals needs to be converted into digital signals by an analog-to-digital converter to facilitate subsequent signal processing and recognition. Therefore, the operating principle of the analog-to-digital converter is introduced. We also show implementation examples and measurement results of low-power low-voltage analog-to-digital converters for biomedical applications.
Book Synopsis Low-power Successive Approximation Analog to Digital Converter with Digital Calibration by : Wei Li
Download or read book Low-power Successive Approximation Analog to Digital Converter with Digital Calibration written by Wei Li and published by . This book was released on 2014 with total page 73 pages. Available in PDF, EPUB and Kindle. Book excerpt: IC designers are continuously facing the challenges from reduced CMOS feature sizes and supply voltages. ADCs that deliver satisfactory resolutions/speeds while utilizing the state-of-the-art technologies to save power are in high demand. The analog circuits are more and more assisted by various digital calibration techniques to get boosted performances. This dissertation is focused on a low-power 12-bit 12.5-MS/s successive approximation (SAR) ADC with a couple of calibration schemes. The performances of the proposed SAR ADC are enhanced in two directions. To reduce the power dissipation, a power saving strategy has been proposed. Also, several foreground calibration methods for SAR ADCs have been proposed to reduce power dissipation and enhance conversion accuracy. The design was fabricated in 40nm CMOS technology. Measurement results after calibration showed a SFDR of 82.2 dB, and a THD improvement of 22.5 dB. Finally, two new schemes to realize teraohm on-chip resistance are presented. One of the schemes utilizes a switched-capacitor array, and the other utilizes a switch-capacitor ladder. Using these schemes, large resistances can be fabricated with standard CMOS process in an affordable chip area.
