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Design Of A High Speed Folding And Interpolation Analog To Digital Converter Implemented In 018 Um Sige Bicmos Process
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Book Synopsis Design of a High Speed Folding and Interpolation Analog to Digital Converter Implemented in 0.18 Um SiGe BiCMOS Process by : Quincy K. L. Fung
Download or read book Design of a High Speed Folding and Interpolation Analog to Digital Converter Implemented in 0.18 Um SiGe BiCMOS Process written by Quincy K. L. Fung and published by . This book was released on 2008 with total page 194 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis Design of a High Speed Folding and Interpolation Analog to Digital Converter Implemented in 0.18 Micrometer Silicon Germanide BiCMOS Process by : Quincy Kwan-Lun Fung
Download or read book Design of a High Speed Folding and Interpolation Analog to Digital Converter Implemented in 0.18 Micrometer Silicon Germanide BiCMOS Process written by Quincy Kwan-Lun Fung and published by . This book was released on 2008 with total page 194 pages. Available in PDF, EPUB and Kindle. Book excerpt: This thesis describes the design and implementation of an 8 bit, 2 GSamples/s analog to digital converter for a 0.18 mum SiGe BiCMOS process with a unity gain cut off frequency of 60 GHz. This folding and interpolation ADC consists of a highly linear track-and-hold amplifier (THA) with 10 bit resolution, a differential resistor ladder, four folding amplifiers, an interpolation stage, a comparator array, a digital encoder with bubble error correction scheme and a coarse quantizer. The microchip area is 3.0 x 3.4 mm2 including pads and buffer circuits. Simulation results show that this ADC has a maximum signal-to-noise and distortion ratio (SNDR) of 48.9 dB corresponding to a 7.5 effective number of bits (ENOB) and an effective resolution bandwidth (ERBW) of 700MHz. The circuit demonstrates a maximum differential nonlinearity (DNL) and integral nonlinearity (INL) of 0.4 and 0.8 LSB, respectively while consuming 3.1W from a single 3.5 V supply.
Book Synopsis Design of High Speed Folding and Interpolating Analog-to-digital Converter by : Yunchu Li
Download or read book Design of High Speed Folding and Interpolating Analog-to-digital Converter written by Yunchu Li and published by . This book was released on 2004 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: High-speed and low resolution analog-to-digital converters (ADC) are key elements in the read channel of optical and magnetic data storage systems. The required resolution is about 6-7 bits while the sampling rate and effective resolution bandwidth requirements increase with each generation of storage system. Folding is a technique to reduce the number of comparators used in the flash architecture. By means of an analog preprocessing circuit in folding A/D converters the number of comparators can be reduced significantly. Folding architectures exhibit low power and low latency as well as the ability to run at high sampling rates. Folding ADCs employing interpolation schemes to generate extra folding waveforms are called "Folding and Interpolating ADC" (F & I ADC). The aim of this research is to increase the input bandwidth of high speed conversion, and low latency F & I ADC. Behavioral models are developed to analyze the bandwidth limitation at the architecture level. A front-end sample-and-hold unit is employed to tackle the frequency multiplication problem, which is intrinsic for all F & I ADCs. Current-mode signal processing is adopted to increase the bandwidth of the folding amplifiers and interpolators, which are the bottleneck of the whole system. An operational transconductance amplifier (OTA) based folding amplifier, current mirror-based interpolator, very low impedance fast current comparator are proposed and designed to carry out the current-mode signal processing. A new bit synchronization scheme is proposed to correct the error caused by the delay difference between the coarse and fine channels. A prototype chip was designed and fabricated in 0.35 ơm CMOS process to verify the ideas. The S/H and F & I ADC prototype is realized in 0.35 [mu]m double-poly CMOS process (only one poly is used). Integral nonlinearity (INL) is 1.0 LSB and Differential nonlinearity (DNL) is 0.6 LSB at 110 KHz. The ADC occupies 1.2mm2 active area and dissipates 200mW (excluding 70mW of S/H) from 3.3V supply. At 300MSPS sampling rate, the ADC achieves no less than 6 ENOB with input signal lower than 60MHz. It has the highest input bandwidth of 60MHz reported in the literature for this type of CMOS ADC with similar resolution and sample rate.
Book Synopsis A High-speed Cascaded Folding and Interpolating A/D Converter by : Yanlok Charlotte Lau
Download or read book A High-speed Cascaded Folding and Interpolating A/D Converter written by Yanlok Charlotte Lau and published by . This book was released on 2003 with total page 86 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis Low-Power High-Resolution Analog to Digital Converters by : Amir Zjajo
Download or read book Low-Power High-Resolution Analog to Digital Converters written by Amir Zjajo and published by Springer Science & Business Media. This book was released on 2010-10-29 with total page 311 pages. Available in PDF, EPUB and Kindle. Book excerpt: With the fast advancement of CMOS fabrication technology, more and more signal-processing functions are implemented in the digital domain for a lower cost, lower power consumption, higher yield, and higher re-configurability. This has recently generated a great demand for low-power, low-voltage A/D converters that can be realized in a mainstream deep-submicron CMOS technology. However, the discrepancies between lithography wavelengths and circuit feature sizes are increasing. Lower power supply voltages significantly reduce noise margins and increase variations in process, device and design parameters. Consequently, it is steadily more difficult to control the fabrication process precisely enough to maintain uniformity. The inherent randomness of materials used in fabrication at nanoscopic scales means that performance will be increasingly variable, not only from die-to-die but also within each individual die. Parametric variability will be compounded by degradation in nanoscale integrated circuits resulting in instability of parameters over time, eventually leading to the development of faults. Process variation cannot be solved by improving manufacturing tolerances; variability must be reduced by new device technology or managed by design in order for scaling to continue. Similarly, within-die performance variation also imposes new challenges for test methods. In an attempt to address these issues, Low-Power High-Resolution Analog-to-Digital Converters specifically focus on: i) improving the power efficiency for the high-speed, and low spurious spectral A/D conversion performance by exploring the potential of low-voltage analog design and calibration techniques, respectively, and ii) development of circuit techniques and algorithms to enhance testing and debugging potential to detect errors dynamically, to isolate and confine faults, and to recover errors continuously. The feasibility of the described methods has been verified by measurements from the silicon prototypes fabricated in standard 180nm, 90nm and 65nm CMOS technology.
Book Synopsis An 8-bit, 12.5GS/s Folding-interpolating Analog-to-digital Converter by : Shohreh Ghetmiri
Download or read book An 8-bit, 12.5GS/s Folding-interpolating Analog-to-digital Converter written by Shohreh Ghetmiri and published by . This book was released on 2009 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis An 8-Bit, 1-Gsample/s Folding-Interpolating Analog-to-Digital Converter by : Wei An
Download or read book An 8-Bit, 1-Gsample/s Folding-Interpolating Analog-to-Digital Converter written by Wei An and published by . This book was released on 2000 with total page 0 pages. Available in PDF, EPUB and Kindle. Book excerpt: This thesis deals with the design and implementation of an 8-bit, 1-Gsample/s folding-interpolating analog-to-digital converter using a conventional 0.5 [mu]m self-aligned, double polysilicon bipolar process with maximum unity gain cutoff frequency fT of 25GHz. The high-speed and high-resolution A/D converter has applications in direct IF sampling receivers for wideband communications systems. The folding-interpolating architecture offers an optimum solution for Gsample/s, high-resolution A/D converters in terms of system complexity, power dissipation and chip area. The use of a silicon bipolar process allows the integration of Gsample/s ADCs with DSP systems usually realized by silicon CMOS or BiCMOS processes. The 8-bit, 1-Gsample/s A/D converter consists of a reference ladder; four folding blocks for the fine quantizer and one folding block for the coarse quantizer; interpolation resistive strings; a comparator array; a digital encoder including an EXOR array, an error-correction stage, and a 31-to-5 OR ROM; and a coarse quantizer. All circuit blocks are integrated on one chip. The chip area of the circuitry is 2.5mm x 3.5mm including bonding pads. The converter exhibits a better than 7-bit ENOB with an input signal frequency of 200MHz and at a sampling rate of 1-Gsample/s The maximum power dissipation of the ADC is 2.5W using a 5-V power supply.
Book Synopsis Design of Folding and Interpolation Stages for a 1-GSample/s, 10-bit A/D Converter in SiGe BiCMOS Technology by : Chih-Yi Kuan
Download or read book Design of Folding and Interpolation Stages for a 1-GSample/s, 10-bit A/D Converter in SiGe BiCMOS Technology written by Chih-Yi Kuan and published by . This book was released on 2006 with total page 108 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis Design of a High Speed Analog-to-digital Converter by : Robert James Sherwood
Download or read book Design of a High Speed Analog-to-digital Converter written by Robert James Sherwood and published by . This book was released on 1970 with total page 186 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis Top-Down Design of High-Performance Sigma-Delta Modulators by : Fernando Medeiro
Download or read book Top-Down Design of High-Performance Sigma-Delta Modulators written by Fernando Medeiro and published by Springer Science & Business Media. This book was released on 1998-11-30 with total page 314 pages. Available in PDF, EPUB and Kindle. Book excerpt: The interest for :I:~ modulation-based NO converters has significantly increased in the last years. The reason for that is twofold. On the one hand, unlike other converters that need accurate building blocks to obtain high res olution, :I:~ converters show low sensitivity to the imperfections of their building blocks. This is achieved through extensive use of digital signal pro cessing - a desirable feature regarding the implementation of NO interfaces in mainstream CMOS technologies which are better suited for implementing fast, dense, digital circuits than accurate analog circuits. On the other hand, the number of applications with industrial interest has also grown. In fact, starting from the earliest in the audio band, today we can find :I:~ converters in a large variety of NO interfaces, ranging from instrumentation to commu nications. These advances have been supported by a number of research works that have lead to a considerably large amount of published papers and books cov ering different sub-topics: from purely theoretical aspects to architecture and circuit optimization. However, so much material is often difficultly digested by those unexperienced designers who have been committed to developing a :I:~ converter, mainly because there is a lack of methodology. In our view, a clear methodology is necessary in :I:~ modulator design because all related tasks are rather hard.
Book Synopsis A Digital-to-analog Conversion Circuit Using Third-order Polynomial Interpolation by : William P. Dotson
Download or read book A Digital-to-analog Conversion Circuit Using Third-order Polynomial Interpolation written by William P. Dotson and published by . This book was released on 1972 with total page 66 pages. Available in PDF, EPUB and Kindle. Book excerpt: Zero- and third-order digital-to-analog conversion techniques are described, and the theoretical error performances are compared. The design equations and procedures for constructing a third-order digital-to-analog converter by using analog design elements are presented. Both a zero- and a third-order digital-to-analog converter were built, and the performances are compared with various signal inputs.
Book Synopsis A High-speed, Folding, Analog-to-digital Converter by : Paul Louis Mangione
Download or read book A High-speed, Folding, Analog-to-digital Converter written by Paul Louis Mangione and published by . This book was released on 1994 with total page 200 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis Design of a CMOS 6-bit Folding and Interpolating Analog to Digital Converter by : Song Liu
Download or read book Design of a CMOS 6-bit Folding and Interpolating Analog to Digital Converter written by Song Liu and published by . This book was released on 1999 with total page 56 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis Millimeter-Wave Analog to Digital Converters: Technology Challenges and Architectures by : Shahriar Shahramian
Download or read book Millimeter-Wave Analog to Digital Converters: Technology Challenges and Architectures written by Shahriar Shahramian and published by . This book was released on 2011 with total page 250 pages. Available in PDF, EPUB and Kindle. Book excerpt: While data converters have been around for nearly nighty years, mm-wave data con- verters are still in their infancy. Only recently the 40-GHz sampling barrier was broken with the introduction of the next generation high-speed sampling oscilloscopes. Mean- while, data communication is the main driving force behind mm-wave data converter development. As with any mm-wave circuit, designers must go beyond simply relying on technology advancement to archives acceptable performance. Careful device and passive modeling is critical and systematic design methodology may offer repeatable and scalable mm-wave designs.In this thesis the design methodology and architectural challenges of mm-wave ADCs are explored. Some of the fundamental mm-wave ADC building blocks such as track and hold amplifers, data distribution networks and flip-flops are implemented in SiGe BiCMOS and CMOS technologies and characterized. Several record breaking circuits are presented along with systematic design methodology. The impact of these circuit blocks on the performance of the next generation ADCs is studied and experimentally verified using a 35-GS/s, 4-bit ADC-DAC chain implemented in a SiGe BiCMOS technology.
Book Synopsis Design of an 8-bit, Pipelined, Analog-to-digital Converter Implemented in a 0.5-um CMOS Process by :
Download or read book Design of an 8-bit, Pipelined, Analog-to-digital Converter Implemented in a 0.5-um CMOS Process written by and published by . This book was released on 2006 with total page 284 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis Design Features of a Transistorized, High Speed Analog-to-digital Converter. by : Wade E Clarke
Download or read book Design Features of a Transistorized, High Speed Analog-to-digital Converter. written by Wade E Clarke and published by Hassell Street Press. This book was released on 2023-07-18 with total page 0 pages. Available in PDF, EPUB and Kindle. Book excerpt: Design Features of a Transistorized High Speed Analog-to-Digital Converter is a technical report that describes the design of a high-speed electronic device. The report includes detailed information on the circuitry and components used in the device, as well as performance data and design considerations. This work has been selected by scholars as being culturally important, and is part of the knowledge base of civilization as we know it. This work is in the "public domain in the United States of America, and possibly other nations. Within the United States, you may freely copy and distribute this work, as no entity (individual or corporate) has a copyright on the body of the work. Scholars believe, and we concur, that this work is important enough to be preserved, reproduced, and made generally available to the public. We appreciate your support of the preservation process, and thank you for being an important part of keeping this knowledge alive and relevant.
Book Synopsis The Design of Low-Voltage, Low-Power Sigma-Delta Modulators by : Shahriar Rabii
Download or read book The Design of Low-Voltage, Low-Power Sigma-Delta Modulators written by Shahriar Rabii and published by Springer. This book was released on 1999 with total page 214 pages. Available in PDF, EPUB and Kindle. Book excerpt: Oversampling techniques based on sigma-delta modulation are widely used to implement the analog/digital interfaces in CMOS VLSI technologies. This approach is relatively insensitive to imperfections in the manufacturing process and offers numerous advantages for the realization of high-resolution analog-to-digital (A/D) converters in the low-voltage environment that is increasingly demanded by advanced VLSI technologies and by portable electronic systems. In The Design of Low-Voltage, Low-Power Sigma-Delta Modulators, an analysis of power dissipation in sigma-delta modulators is presented, and a low-voltage implementation of a digital-audio performance A/D converter based on the results of this analysis is described. Although significant power savings can typically be achieved in digital circuits by reducing the power supply voltage, the power dissipation in analog circuits actually tends to increase with decreasing supply voltages. Oversampling architectures are a potentially power-efficient means of implementing high-resolution A/D converters because they reduce the number and complexity of the analog circuits in comparison with Nyquist-rate converters. In fact, it is shown that the power dissipation of a sigma-delta modulator can approach that of a single integrator with the resolution and bandwidth required for a given application. In this research the influence of various parameters on the power dissipation of the modulator has been evaluated and strategies for the design of a power-efficient implementation have been identified. The Design of Low-Voltage, Low-Power Sigma-Delta Modulators begins with an overview of A/D conversion, emphasizing sigma-delta modulators. It includes a detailed analysis of noise in sigma-delta modulators, analyzes power dissipation in integrator circuits, and addresses practical issues in the circuit design and testing of a high-resolution modulator. The Design of Low-Voltage, Low-Power Sigma-Delta Modulators will be of interest to practicing engineers and researchers in the areas of mixed-signal and analog integrated circuit design.
