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Design And Optimization Of Hardware Accelerator Design
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Book Synopsis Design and Optimization of Hardware Accelerator Design by : Navateja Alla
Download or read book Design and Optimization of Hardware Accelerator Design written by Navateja Alla and published by . This book was released on 2020 with total page 213 pages. Available in PDF, EPUB and Kindle. Book excerpt: Deep neural networks have become prominent in solving many real-life problems. However, they need to rely on learning patterns of data. As the demand for such services grows, merely scaling-out the number of accelerators is not economically cost-effective. Although multi-tenancy has propelled data center scalability, it has not been a primary factor in designing DNN accelerators due to the arms race for higher speed and efficiency. A new architecture is proposed which helps in spatially co-locating multiple DNN inference services on the same hardware, offering simultaneous multi-tenant DNN acceleration.
Book Synopsis Efficient Processing of Deep Neural Networks by : Vivienne Sze
Download or read book Efficient Processing of Deep Neural Networks written by Vivienne Sze and published by Springer Nature. This book was released on 2022-05-31 with total page 254 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book provides a structured treatment of the key principles and techniques for enabling efficient processing of deep neural networks (DNNs). DNNs are currently widely used for many artificial intelligence (AI) applications, including computer vision, speech recognition, and robotics. While DNNs deliver state-of-the-art accuracy on many AI tasks, it comes at the cost of high computational complexity. Therefore, techniques that enable efficient processing of deep neural networks to improve key metrics—such as energy-efficiency, throughput, and latency—without sacrificing accuracy or increasing hardware costs are critical to enabling the wide deployment of DNNs in AI systems. The book includes background on DNN processing; a description and taxonomy of hardware architectural approaches for designing DNN accelerators; key metrics for evaluating and comparing different designs; features of DNN processing that are amenable to hardware/algorithm co-design to improve energy efficiency and throughput; and opportunities for applying new technologies. Readers will find a structured introduction to the field as well as formalization and organization of key concepts from contemporary work that provide insights that may spark new ideas.
Book Synopsis Research Infrastructures for Hardware Accelerators by : Yakun Sophia Shao
Download or read book Research Infrastructures for Hardware Accelerators written by Yakun Sophia Shao and published by Morgan & Claypool Publishers. This book was released on 2015-11-01 with total page 101 pages. Available in PDF, EPUB and Kindle. Book excerpt: Hardware acceleration in the form of customized datapath and control circuitry tuned to specific applications has gained popularity for its promise to utilize transistors more efficiently. Historically, the computer architecture community has focused on general-purpose processors, and extensive research infrastructure has been developed to support research efforts in this domain. Envisioning future computing systems with a diverse set of general-purpose cores and accelerators, computer architects must add accelerator-related research infrastructures to their toolboxes to explore future heterogeneous systems. This book serves as a primer for the field, as an overview of the vast literature on accelerator architectures and their design flows, and as a resource guidebook for researchers working in related areas.
Book Synopsis Artificial Intelligence Hardware Design by : Albert Chun-Chen Liu
Download or read book Artificial Intelligence Hardware Design written by Albert Chun-Chen Liu and published by John Wiley & Sons. This book was released on 2021-08-23 with total page 244 pages. Available in PDF, EPUB and Kindle. Book excerpt: ARTIFICIAL INTELLIGENCE HARDWARE DESIGN Learn foundational and advanced topics in Neural Processing Unit design with real-world examples from leading voices in the field In Artificial Intelligence Hardware Design: Challenges and Solutions, distinguished researchers and authors Drs. Albert Chun Chen Liu and Oscar Ming Kin Law deliver a rigorous and practical treatment of the design applications of specific circuits and systems for accelerating neural network processing. Beginning with a discussion and explanation of neural networks and their developmental history, the book goes on to describe parallel architectures, streaming graphs for massive parallel computation, and convolution optimization. The authors offer readers an illustration of in-memory computation through Georgia Tech’s Neurocube and Stanford’s Tetris accelerator using the Hybrid Memory Cube, as well as near-memory architecture through the embedded eDRAM of the Institute of Computing Technology, the Chinese Academy of Science, and other institutions. Readers will also find a discussion of 3D neural processing techniques to support multiple layer neural networks, as well as information like: A thorough introduction to neural networks and neural network development history, as well as Convolutional Neural Network (CNN) models Explorations of various parallel architectures, including the Intel CPU, Nvidia GPU, Google TPU, and Microsoft NPU, emphasizing hardware and software integration for performance improvement Discussions of streaming graph for massive parallel computation with the Blaize GSP and Graphcore IPU An examination of how to optimize convolution with UCLA Deep Convolutional Neural Network accelerator filter decomposition Perfect for hardware and software engineers and firmware developers, Artificial Intelligence Hardware Design is an indispensable resource for anyone working with Neural Processing Units in either a hardware or software capacity.
Book Synopsis Field Computation for Accelerator Magnets by : Stephan Russenschuck
Download or read book Field Computation for Accelerator Magnets written by Stephan Russenschuck and published by John Wiley & Sons. This book was released on 2011-02-08 with total page 778 pages. Available in PDF, EPUB and Kindle. Book excerpt: Written by a leading expert on the electromagnetic design and engineering of superconducting accelerator magnets, this book offers the most comprehensive treatment of the subject to date. In concise and easy-to-read style, the author lays out both the mathematical basis for analytical and numerical field computation and their application to magnet design and manufacture. Of special interest is the presentation of a software-based design process that has been applied to the entire production cycle of accelerator magnets from the concept phase to field optimization, production follow-up, and hardware commissioning. Included topics: Technological challenges for the Large Hadron Collider at CERN Algebraic structures and vector fields Classical vector analysis Foundations of analytical field computation Fields and Potentials of line currents Harmonic fields The conceptual design of iron- and coil-dominated magnets Solenoids Complex analysis methods for magnet design Elementary beam optics and magnet polarities Numerical field calculation using finite- and boundary-elements Mesh generation Time transient effects in superconducting magnets, including superconductor magnetization and cable eddy-currents Quench simulation and magnet protection Mathematical optimization techniques using genetic and deterministic algorithms Practical experience from the electromagnetic design of the LHC magnets illustrates the analytical and numerical concepts, emphasizing the relevance of the presented methods to a great many applications in electrical engineering. The result is an indispensable guide for high-energy physicists, electrical engineers, materials scientists, applied mathematicians, and systems engineers.
Book Synopsis Hardware Accelerator Systems for Artificial Intelligence and Machine Learning by :
Download or read book Hardware Accelerator Systems for Artificial Intelligence and Machine Learning written by and published by Academic Press. This book was released on 2021-03-28 with total page 416 pages. Available in PDF, EPUB and Kindle. Book excerpt: Hardware Accelerator Systems for Artificial Intelligence and Machine Learning, Volume 122 delves into arti?cial Intelligence and the growth it has seen with the advent of Deep Neural Networks (DNNs) and Machine Learning. Updates in this release include chapters on Hardware accelerator systems for artificial intelligence and machine learning, Introduction to Hardware Accelerator Systems for Artificial Intelligence and Machine Learning, Deep Learning with GPUs, Edge Computing Optimization of Deep Learning Models for Specialized Tensor Processing Architectures, Architecture of NPU for DNN, Hardware Architecture for Convolutional Neural Network for Image Processing, FPGA based Neural Network Accelerators, and much more. Updates on new information on the architecture of GPU, NPU and DNN Discusses In-memory computing, Machine intelligence and Quantum computing Includes sections on Hardware Accelerator Systems to improve processing efficiency and performance
Book Synopsis Compact and Fast Machine Learning Accelerator for IoT Devices by : Hantao Huang
Download or read book Compact and Fast Machine Learning Accelerator for IoT Devices written by Hantao Huang and published by Springer. This book was released on 2018-12-07 with total page 149 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book presents the latest techniques for machine learning based data analytics on IoT edge devices. A comprehensive literature review on neural network compression and machine learning accelerator is presented from both algorithm level optimization and hardware architecture optimization. Coverage focuses on shallow and deep neural network with real applications on smart buildings. The authors also discuss hardware architecture design with coverage focusing on both CMOS based computing systems and the new emerging Resistive Random-Access Memory (RRAM) based systems. Detailed case studies such as indoor positioning, energy management and intrusion detection are also presented for smart buildings.
Book Synopsis Learning Optimizations for Hardware Accelerated Designs by : Pingfan Meng
Download or read book Learning Optimizations for Hardware Accelerated Designs written by Pingfan Meng and published by . This book was released on 2016 with total page 142 pages. Available in PDF, EPUB and Kindle. Book excerpt: Many emerging applications require hardware acceleration due to their growing computational intensities. These accelerated designs use heterogeneous hardware, such as GPUs, FPGAs and multi-core CPUs to process the intensive computations at a higher rate. The first part of this work provides two paradigms of hardware accelerated biomedical applications. These paradigms achieved 115X and 273X speedups respectively. Developing these paradigms taught us that, in order to efficiently utilize the heterogeneous accelerators, the designer needs to carefully investigate which device is the most suitable accelerator for a particular computing task. In addition, the designer needs to effectively optimize the computations to fully exploit the computing power of the selected accelerator. This process is called design space exploration (DSE). Heterogeneous DSE requires multiple programming skills for these different types of devices. In recent years, there is a trend to use one unified programming language for multiple heterogeneous devices. The SDKs and hardware synthesis tools have enabled OpenCL as one unified language to program heterogeneous devices including GPUs, FPGAs, and multi-core CPUs. However, one major bottleneck for DSE still exists. In contrast to GPU and CPU OpenCL code compilation, which only consumes several milliseconds, implementing OpenCL designs on a FPGA requires hours of compilation time. Moreover, merely tuning a few programming parameters in the OpenCL code will result in an abundance of possible designs. Implementing all these designs requires months of compilation time. Exploring the FPGA design space with brute force is therefore impractical. The second part of this work addresses this issue by providing a machine learning approach for automatic DSE. This machine learning approach automatically identifies the optimal designs by learning from a few training samples. In comparison with other state-of-the-art machine learning frameworks, this approach reduces the amount of hardware compilations by 3.28X, which is equivalent to hundreds of compute hours. This work also provides a data mining method that enables the machine to automatically use the estimation data to replace the time consuming end-to-end FPGA training samples for DSE. Mining these estimation data further reduces the amount of hardware compilations by 1.26X.
Book Synopsis Accelerators for Convolutional Neural Networks by : Arslan Munir
Download or read book Accelerators for Convolutional Neural Networks written by Arslan Munir and published by John Wiley & Sons. This book was released on 2023-10-31 with total page 308 pages. Available in PDF, EPUB and Kindle. Book excerpt: Accelerators for Convolutional Neural Networks Comprehensive and thorough resource exploring different types of convolutional neural networks and complementary accelerators Accelerators for Convolutional Neural Networks provides basic deep learning knowledge and instructive content to build up convolutional neural network (CNN) accelerators for the Internet of things (IoT) and edge computing practitioners, elucidating compressive coding for CNNs, presenting a two-step lossless input feature maps compression method, discussing arithmetic coding -based lossless weights compression method and the design of an associated decoding method, describing contemporary sparse CNNs that consider sparsity in both weights and activation maps, and discussing hardware/software co-design and co-scheduling techniques that can lead to better optimization and utilization of the available hardware resources for CNN acceleration. The first part of the book provides an overview of CNNs along with the composition and parameters of different contemporary CNN models. Later chapters focus on compressive coding for CNNs and the design of dense CNN accelerators. The book also provides directions for future research and development for CNN accelerators. Other sample topics covered in Accelerators for Convolutional Neural Networks include: How to apply arithmetic coding and decoding with range scaling for lossless weight compression for 5-bit CNN weights to deploy CNNs in extremely resource-constrained systems State-of-the-art research surrounding dense CNN accelerators, which are mostly based on systolic arrays or parallel multiply-accumulate (MAC) arrays iMAC dense CNN accelerator, which combines image-to-column (im2col) and general matrix multiplication (GEMM) hardware acceleration Multi-threaded, low-cost, log-based processing element (PE) core, instances of which are stacked in a spatial grid to engender NeuroMAX dense accelerator Sparse-PE, a multi-threaded and flexible CNN PE core that exploits sparsity in both weights and activation maps, instances of which can be stacked in a spatial grid for engendering sparse CNN accelerators For researchers in AI, computer vision, computer architecture, and embedded systems, along with graduate and senior undergraduate students in related programs of study, Accelerators for Convolutional Neural Networks is an essential resource to understanding the many facets of the subject and relevant applications.
Book Synopsis AI for Design Optimization and Design for AI Acceleration by : Uday Bhanu Sharma Mallappa
Download or read book AI for Design Optimization and Design for AI Acceleration written by Uday Bhanu Sharma Mallappa and published by . This book was released on 2022 with total page 0 pages. Available in PDF, EPUB and Kindle. Book excerpt: Integrated circuit (IC) design at the scale of billions of circuit elements would be unimaginable without the software and services from the Electronic Design Automation (EDA) industry. However, today, the designers using these EDA tools and flows are confronted by long runtimes, high design costs and low power, performance and area (PPA) gains when transitioning to the latest process nodes. The long tool-runtimes and high tool-license costs make it prohibitively expensive for a thorough design-space exploration. Furthermore, pessimistic margins introduced at various stages of the EDA flow, to balance the accuracy-runtime tradeoff, result in suboptimal design implementations. To counter these issues and keep up with the pace of PPA expectations from the market, the dissertation contributes to two promising opportunities at the top of the computing stack; (1) algorithmic improvements and (2) domain-specialized hardware. For algorithmic contributions, we exploit AI-based techniques (i) to reduce the design and schedule costs of advanced node IC design, and (ii) to efficiently search for optimal design implementations. A significant portion of the design cycle is spent on the static timing analysis (STA) at multiple corners and multiple modes (MCMM). To address the schedule costs of STA engines, we propose a learning model to accurately predict expensive path-based analysis (PBA) results from pessimistic graph-based analysis (GBA). We also devise a MCMM timing model using learning-based techniques, to predict accurate timing results at unobserved signoff corners, using timing results from a small subset of corners. Our PBA-GBA model reduces the maximum PBA-GBA divergence from 50.78ps to 39.46ps, for a 350K-instance design in 28nm FDSOI foundry. Our MCMM timing prediction model uses timing results from 10 observed corners, to predict timing results at the remaining 48 unobserved corners with less than 0.5% relative root mean squared error (RMSE), for a 1M-instance design in 16nm enablement. Besides STA, two most important and critical phases of the IC design cycle are the placement of standard cells, and the routing tasks at various abstraction levels. To demonstrate the use of learning-based models for efficient search of optimal placement implementation, we propose a reinforcement learning (RL)-based framework RLPlace for the task of detailed placement optimization. With global placement output of two critical IPs as the start point, RLPlace achieves up to 1.35% half-perimeter wirelength (HPWL) improvement as compared to the commercial tool's detailed placement results. To efficiently search for optimal routing solutions in network-based communication systems, we propose a SMT-based framework to jointly determine routing and virtual channel (VC) assignment solutions in network-on-chip (NOC) design. Our novel formulation enables better deadlock-free performance, achieving up to 30% better performance than the state-of-the-art application-aware oblivious routing algorithms. We propose two novel hardware accelerators for image classification tasks, to exemplify the performance and energy benefits of domain-specialized hardware. To alleviate the computation and energy burden of neural network inference, we focus on two key areas; (i) skipping unnecessary computations, and (i) maximizing the reuse of redundant computations. Our TermiNETor framework skips ineffectual computations during the inference of image classification tasks. TermiNETor relies on bit-serial weight processing, to dynamically predict and skip the computations that are unnecessary for downstream computations. Our TermiNETor framework achieves up to 1.7x reduction of operation count compared to non-skipping baseline without accuracy degradation, and the hardware implementation of TermiNETor framework improves the average energy efficiency by 3.84x over SCNN [6], and by 1.98x over FuseKNA [7]. Our second accelerator PatterNet demonstrates the performance and energy benefits of reusing redundant computations during the inference phase of image classification. PatterNet is based on patterned neural networks for computation reuse, and supported with a novel pattern-stationary architecture. With similar accuracy results, our PatterNet accelerator reduces the memory and operation count up to 80.2% and 73.1%, respectively, and 107x more energy efficient compared to Nvidia 1080 GTX. We demonstrate the silicon implementation of PatterNet and TermiNETor accelerators in TSMC40nm foundry enablement.
Book Synopsis VLSI and Hardware Implementations using Modern Machine Learning Methods by : Sandeep Saini
Download or read book VLSI and Hardware Implementations using Modern Machine Learning Methods written by Sandeep Saini and published by CRC Press. This book was released on 2021-12-30 with total page 329 pages. Available in PDF, EPUB and Kindle. Book excerpt: Machine learning is a potential solution to resolve bottleneck issues in VLSI via optimizing tasks in the design process. This book aims to provide the latest machine-learning–based methods, algorithms, architectures, and frameworks designed for VLSI design. The focus is on digital, analog, and mixed-signal design techniques, device modeling, physical design, hardware implementation, testability, reconfigurable design, synthesis and verification, and related areas. Chapters include case studies as well as novel research ideas in the given field. Overall, the book provides practical implementations of VLSI design, IC design, and hardware realization using machine learning techniques. Features: Provides the details of state-of-the-art machine learning methods used in VLSI design Discusses hardware implementation and device modeling pertaining to machine learning algorithms Explores machine learning for various VLSI architectures and reconfigurable computing Illustrates the latest techniques for device size and feature optimization Highlights the latest case studies and reviews of the methods used for hardware implementation This book is aimed at researchers, professionals, and graduate students in VLSI, machine learning, electrical and electronic engineering, computer engineering, and hardware systems.
Book Synopsis Programmable Hardware Acceleration by : Vinay Gangadhar
Download or read book Programmable Hardware Acceleration written by Vinay Gangadhar and published by . This book was released on 2017 with total page 160 pages. Available in PDF, EPUB and Kindle. Book excerpt: The rising dark silicon problem and the waning benefits of device scaling has caused a push towards specialization and hardware acceleration in last few years. Recently, computer architects both in industry and academia have followed the trend of building custom high-performance hardware engines for individual application domains, generally called as Domain-Specific Accelerators (DSAs). DSAs have been shown to achieve 10 to 1,000 times performance and energy efficiency improvements over general-purpose and data-parallel architectures for various application domains like machine learning, computer vision, databases and others. While providing these huge benefits, DSAs sacrifice programmability for efficiency and are prone to obsoletion due to domain volatility. The stark trade-offs between efficiency and generality at these two extremes poses an interesting question: Is it possible to have an architecture which has the best of both -- programmability and efficiency, and how close can we get to such a design? This dissertation explores how far the efficiency of a programmable architecture can be pushed, and whether it can come close to the performance, energy, and area efficiency of a domain-specific based approach. We specifically propose a type of hardware acceleration called "Programmable Hardware Acceleration", with the design, implementation, and evaluation of a hardware accelerator which is programmable using an efficient hardware-software interface and yet achieve efficiency close to DSAs. This work has several observations and key findings. First, we rely on the insight that 'acceleratable' algorithms have common specialization principles and most of the DSAs employ these. Second, these specialization principles can be exploited in a hardware architecture with a right composure of programmable and configurable microarchitectural mechanisms to arrive at a generic programmable hardware accelerator design. Third, the same primitives can also be exposed to the programmers as a hardware-software interface to take benefit of the programmable acceleration. Our evaluation and analysis suggest that a programmable hardware accelerator can achieve performance as close as DSAs with only 2x overheads in area and power. In summary, this work shows a principled approach in building hardware accelerators by pushing the limits of their efficiency while still retaining the programmability.
Book Synopsis FPGA-BASED Hardware Accelerators by : Iouliia Skliarova
Download or read book FPGA-BASED Hardware Accelerators written by Iouliia Skliarova and published by Springer. This book was released on 2019-05-30 with total page 245 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book suggests and describes a number of fast parallel circuits for data/vector processing using FPGA-based hardware accelerators. Three primary areas are covered: searching, sorting, and counting in combinational and iterative networks. These include the application of traditional structures that rely on comparators/swappers as well as alternative networks with a variety of core elements such as adders, logical gates, and look-up tables. The iterative technique discussed in the book enables the sequential reuse of relatively large combinational blocks that execute many parallel operations with small propagation delays. For each type of network discussed, the main focus is on the step-by-step development of the architectures proposed from initial concepts to synthesizable hardware description language specifications. Each type of network is taken through several stages, including modeling the desired functionality in software, the retrieval and automatic conversion of key functions, leading to specifications for optimized hardware modules. The resulting specifications are then synthesized, implemented, and tested in FPGAs using commercial design environments and prototyping boards. The methods proposed can be used in a range of data processing applications, including traditional sorting, the extraction of maximum and minimum subsets from large data sets, communication-time data processing, finding frequently occurring items in a set, and Hamming weight/distance counters/comparators. The book is intended to be a valuable support material for university and industrial engineering courses that involve FPGA-based circuit and system design.
Book Synopsis Embedded Machine Learning for Cyber-Physical, IoT, and Edge Computing by : Sudeep Pasricha
Download or read book Embedded Machine Learning for Cyber-Physical, IoT, and Edge Computing written by Sudeep Pasricha and published by Springer Nature. This book was released on 2023-11-01 with total page 418 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book presents recent advances towards the goal of enabling efficient implementation of machine learning models on resource-constrained systems, covering different application domains. The focus is on presenting interesting and new use cases of applying machine learning to innovative application domains, exploring the efficient hardware design of efficient machine learning accelerators, memory optimization techniques, illustrating model compression and neural architecture search techniques for energy-efficient and fast execution on resource-constrained hardware platforms, and understanding hardware-software codesign techniques for achieving even greater energy, reliability, and performance benefits.
Author :Anirban Sengupta Publisher :Institution of Engineering and Technology ISBN 13 :1839533064 Total Pages :405 pages Book Rating :4.8/5 (395 download)
Book Synopsis Secured Hardware Accelerators for DSP and Image Processing Applications by : Anirban Sengupta
Download or read book Secured Hardware Accelerators for DSP and Image Processing Applications written by Anirban Sengupta and published by Institution of Engineering and Technology. This book was released on 2020-11-12 with total page 405 pages. Available in PDF, EPUB and Kindle. Book excerpt: Written by an acknowledged expert in the field, this book focuses on approaches for designing secure hardware accelerators for digital signal processing and image processing, which are also optimised for performance and efficiency. State-of-the art security and optimization algorithms are presented, and their roles in the design of secured hardware accelerators for DSP, multimedia and image processing applications are explored.
Book Synopsis Mixed-precision NN Accelerator with Neural-hardware Architecture Search by : Yujun Lin (S. M.)
Download or read book Mixed-precision NN Accelerator with Neural-hardware Architecture Search written by Yujun Lin (S. M.) and published by . This book was released on 2020 with total page 65 pages. Available in PDF, EPUB and Kindle. Book excerpt: Neural architecture and hardware architecture co-design is an effective way to enable specialization and acceleration for deep neural networks (DNNs). The design space and its exploration methodology impact efficiency and productivity. However, both architecture designs are challenging. We first propose a mixed-precision accelerator, a highly parameterized architecture that can adapt to different bit widths for different quantized layers with significantly reduced overhead. It efficiently provides a vast design space for both neural and hardware architecture. However, it is difficult to exhaust such an enormous design space by rule-based heuristics. To tackle this problem, we propose a machine learning based design and optimization methodology of a neural network accelerator. It includes the evolution strategy based hardware architecture search and one-shot HyperNet based quantized neural architecture search. Evaluated on existing DNN benchmarks, our mixed-precision accelerator achieves 11.7x, 1.5x speedup and 10.5x, 1.9x energy savings over Eyeriss [3] and BitFusion [35] respectively under the same area, frequency, and process technology. Our machine learning based co-design can compose highly matched neural-hardware architectures and further rival the best human-designed architectures by additional 1.3x speedup and 1.5x energy savings under the same ImageNet accuracy with better sample efficiency.
Book Synopsis Learning in Energy-Efficient Neuromorphic Computing: Algorithm and Architecture Co-Design by : Nan Zheng
Download or read book Learning in Energy-Efficient Neuromorphic Computing: Algorithm and Architecture Co-Design written by Nan Zheng and published by John Wiley & Sons. This book was released on 2019-10-18 with total page 389 pages. Available in PDF, EPUB and Kindle. Book excerpt: Explains current co-design and co-optimization methodologies for building hardware neural networks and algorithms for machine learning applications This book focuses on how to build energy-efficient hardware for neural networks with learning capabilities—and provides co-design and co-optimization methodologies for building hardware neural networks that can learn. Presenting a complete picture from high-level algorithm to low-level implementation details, Learning in Energy-Efficient Neuromorphic Computing: Algorithm and Architecture Co-Design also covers many fundamentals and essentials in neural networks (e.g., deep learning), as well as hardware implementation of neural networks. The book begins with an overview of neural networks. It then discusses algorithms for utilizing and training rate-based artificial neural networks. Next comes an introduction to various options for executing neural networks, ranging from general-purpose processors to specialized hardware, from digital accelerator to analog accelerator. A design example on building energy-efficient accelerator for adaptive dynamic programming with neural networks is also presented. An examination of fundamental concepts and popular learning algorithms for spiking neural networks follows that, along with a look at the hardware for spiking neural networks. Then comes a chapter offering readers three design examples (two of which are based on conventional CMOS, and one on emerging nanotechnology) to implement the learning algorithm found in the previous chapter. The book concludes with an outlook on the future of neural network hardware. Includes cross-layer survey of hardware accelerators for neuromorphic algorithms Covers the co-design of architecture and algorithms with emerging devices for much-improved computing efficiency Focuses on the co-design of algorithms and hardware, which is especially critical for using emerging devices, such as traditional memristors or diffusive memristors, for neuromorphic computing Learning in Energy-Efficient Neuromorphic Computing: Algorithm and Architecture Co-Design is an ideal resource for researchers, scientists, software engineers, and hardware engineers dealing with the ever-increasing requirement on power consumption and response time. It is also excellent for teaching and training undergraduate and graduate students about the latest generation neural networks with powerful learning capabilities.
