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Delay Fault Coverage
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Book Synopsis Delay Fault Testing for VLSI Circuits by : Angela Krstic
Download or read book Delay Fault Testing for VLSI Circuits written by Angela Krstic and published by Springer Science & Business Media. This book was released on 2012-12-06 with total page 201 pages. Available in PDF, EPUB and Kindle. Book excerpt: In the early days of digital design, we were concerned with the logical correctness of circuits. We knew that if we slowed down the clock signal sufficiently, the circuit would function correctly. With improvements in the semiconductor process technology, our expectations on speed have soared. A frequently asked question in the last decade has been how fast can the clock run. This puts significant demands on timing analysis and delay testing. Fueled by the above events, a tremendous growth has occurred in the research on delay testing. Recent work includes fault models, algorithms for test generation and fault simulation, and methods for design and synthesis for testability. The authors of this book, Angela Krstic and Tim Cheng, have personally contributed to this research. Now they do an even greater service to the profession by collecting the work of a large number of researchers. In addition to expounding such a great deal of information, they have delivered it with utmost clarity. To further the reader's understanding many key concepts are illustrated by simple examples. The basic ideas of delay testing have reached a level of maturity that makes them suitable for practice. In that sense, this book is the best x DELAY FAULT TESTING FOR VLSI CIRCUITS available guide for an engineer designing or testing VLSI systems. Tech niques for path delay testing and for use of slower test equipment to test high-speed circuits are of particular interest.
Book Synopsis Delay Fault Coverage by : Mukund Sivaraman
Download or read book Delay Fault Coverage written by Mukund Sivaraman and published by . This book was released on 1996 with total page 17 pages. Available in PDF, EPUB and Kindle. Book excerpt: Abstract: "In this paper, we propose a new and realistic definition of delay fault coverage, based on the percentage of fabricated faulty chips which can be detected as faulty by a given test set. This metric takes into account the probability distribution of delay fault sizes caused by fabrication process effects. Previously, metrics for the effectiveness of a test set for path delay faults have been based on the percentage of paths tested. Also, gate delay fault test quality and coverage metrics which take into account the size of delay faults, and, in some cases, delay fault size distributions, are limited in scope to only single, localized gate delay defects. Moreover, results which show computationally efficient means of determining gate delay fault coverages using such metrics are lacking. In addition to proposing a realistic delay fault coverage metric, we also present a computationally viable scheme for using this metric to estimate the coverage of any given test set for a class of path delay faults caused by distributed fabrication process variations. We use the results for the ISCAS'89 and Logic synthesis'91 benchmark circuits to demonstrate wide discrepancies between distributed path delay fault coverage estimates for robust test sets obtained using our realistic definition, and the ones obtained by using the traditional notion of coverage as the percentage of paths tested."
Book Synopsis Heuristics for Path Delay Fault Coverage Estimation by : Nasrrien Heiluz Gaspar
Download or read book Heuristics for Path Delay Fault Coverage Estimation written by Nasrrien Heiluz Gaspar and published by . This book was released on 1996 with total page 92 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis A Unified Approach for Timing Verification and Delay Fault Testing by : Mukund Sivaraman
Download or read book A Unified Approach for Timing Verification and Delay Fault Testing written by Mukund Sivaraman and published by Springer Science & Business Media. This book was released on 2012-09-17 with total page 164 pages. Available in PDF, EPUB and Kindle. Book excerpt: Large system complexities and operation under tight timing constraints in rapidly shrinking technologies have made it extremely important to ensure correct temporal behavior of modern-day digital circuits, both before and after fabrication. Research in (pre-fabrication) timing verification and (post-fabrication) delay fault testing has evolved along largely disjoint lines in spite of the fact that they share many basic concepts. A Unified Approach for Timing Verification and Delay Fault Testing applies concepts developed in the context of delay fault testing to path sensitization, which allows an accurate timing analysis mechanism to be developed. This path sensitization strategy is further applied for efficient delay fault diagnosis and delay fault coverage estimation. A new path sensitization strategy called Signal Stabilization Time Analysis (SSTA) has been developed based on the fact that primitive PDFs determine the stabilization time of the circuit outputs. This analysis has been used to develop a feasible method of identifying the primitive PDFs in a general multi-level logic circuit. An approach to determine the maximum circuit delay using this primitive PDF identification mechanism is also presented. The Primitive PDF Identification-based Timing Analysis (PITA) approach is proved to determine the maximum floating mode circuit delay exactly under any component delay model, and provides several advantages over previously floating mode timing analyzers. A framework for the diagnosis of circuit failures caused by distributed path delay faults is also presented. A metric to quantify the diagnosability of a path delay fault for a test is also proposed. Finally, the book presents a very realistic metric for delay fault coverage which accounts for delay fault size distributions and is applicable to any delay fault model. A Unified Approach for Timing Verification and Delay Fault Testing will be of interest to university and industry researchers in timing analysis and delay fault testing as well as EDA tool development engineers and design verification engineers dealing with timing issues in ULSI circuits. The book should also be of interest to digital designers and others interested in knowing the state of the art in timing verification and delay fault testing.
Book Synopsis Testability Considerations in Delay Fault Testing by : Mahilchi Milir Vaseekar Kumar
Download or read book Testability Considerations in Delay Fault Testing written by Mahilchi Milir Vaseekar Kumar and published by . This book was released on 2006 with total page 137 pages. Available in PDF, EPUB and Kindle. Book excerpt: In recent years, delay testing has become a very important problem. This dissertation addresses three testability considerations namely, the power consumption, test quality and fault coverage in delay fault testing. The transition fault and the path delay fault models have been used for the purpose of studying these problems. Effective design automation techniques have been proposed using efficient data structures. The exponential number of path delay faults are handled non-enumeratively in all the proposed methods. Experimental results demonstrate the advantage of the proposed techniques over existing methods.
Book Synopsis Test Generation of Crosstalk Delay Faults in VLSI Circuits by : S. Jayanthy
Download or read book Test Generation of Crosstalk Delay Faults in VLSI Circuits written by S. Jayanthy and published by Springer. This book was released on 2018-09-20 with total page 161 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book describes a variety of test generation algorithms for testing crosstalk delay faults in VLSI circuits. It introduces readers to the various crosstalk effects and describes both deterministic and simulation-based methods for testing crosstalk delay faults. The book begins with a focus on currently available crosstalk delay models, test generation algorithms for delay faults and crosstalk delay faults, before moving on to deterministic algorithms and simulation-based algorithms used to test crosstalk delay faults. Given its depth of coverage, the book will be of interest to design engineers and researchers in the field of VLSI Testing.
Book Synopsis Delay Fault Coverage, Test Set Size, and Performance Tradeoffs by : William Kwei-Cheung Lam
Download or read book Delay Fault Coverage, Test Set Size, and Performance Tradeoffs written by William Kwei-Cheung Lam and published by . This book was released on 1992 with total page 26 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis Statistical Coverage Estimation for Path Delay Faults by : Mukund Sivaraman
Download or read book Statistical Coverage Estimation for Path Delay Faults written by Mukund Sivaraman and published by . This book was released on 1995 with total page 19 pages. Available in PDF, EPUB and Kindle. Book excerpt: Abstract: "In this paper, we propose a new and realistic definition of path delay fault coverage, based on the percentage of fabricated faulty chips which can be detected as faulty by a given test set. This metric takes into account the probability distribution of fault sizes caused by fabrication process effects. Previously, metrics for the effectiveness of a test set for path delay faults have been based on the percentage of paths tested. Also, gate delay fault test quality and coverage metrics which take into account fault sizes and, in one case [24], fault size distributions, are limited in scope to only single, localized gate delay defects. Moreover, results which show computationally efficient means of estimating gate delay fault coverages using such metrics are lacking. In addition to proposing a realistic delay fault coverage metric, we also present a computationally viable scheme for using this metric to estimate the coverage of any given test set for path delay faults caused by fabrication process variations. We use the results for the ISCAS'89 and Logic synthesis'91 benchmark circuits to demonstrate wide discrepancies between parametric path delay fault coverage estimates for robust test sets obtained using our realistic definition, and the ones obtained by using the traditional notion of coverage as the percentage of paths tested."
Book Synopsis High Quality Transition and Small Delay Fault ATPG by :
Download or read book High Quality Transition and Small Delay Fault ATPG written by and published by . This book was released on 2004 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: Path selection and generating tests for small delay faults is an important issue in the delay fault area. A novel technique for generating effective vectors for delay defects is the first issue that we have presented in the thesis. The test set achieves high path delay fault coverage to capture small-distributed delay defects and high transition fault coverage to capture gross delay defects. Furthermore, non-robust paths for ATPG are filtered (selected) carefully so that there is a minimum overlap with the already tested robust paths. A relationship between path delay fault model and transition fault model has been observed which helps us reduce the number of non-robust paths considered for test generation. To generate tests for robust and non-robust paths, a deterministic ATPG engine is developed. To deal with small delay faults, we have proposed a new transition fault model called As late As Possible Transition Fault (ALAPTF) Model. The model aims at detecting smaller delays, which will be missed by both the traditional transition fault model and the path delay model. The model makes sure that each transition is launched as late as possible at the fault site, accumulating the small delay defects along its way. Because some transition faults may require multiple paths to be launched, simple path-delay model will miss such faults.
Book Synopsis Low Space Complexity Path Delay Fault Coverage Algorithms by : Mehmet Hadi Güneș
Download or read book Low Space Complexity Path Delay Fault Coverage Algorithms written by Mehmet Hadi Güneș and published by . This book was released on 2004 with total page 148 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis Approximate and Statistical Methods to Complete Delay Fault Coverage by : Keerthinarayan P. Heragu
Download or read book Approximate and Statistical Methods to Complete Delay Fault Coverage written by Keerthinarayan P. Heragu and published by . This book was released on 1994 with total page 150 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis Fault Simulation and Test Generation for Small Delay Faults by : Wangqi Qiu
Download or read book Fault Simulation and Test Generation for Small Delay Faults written by Wangqi Qiu and published by . This book was released on 2006 with total page 130 pages. Available in PDF, EPUB and Kindle. Book excerpt: The ATPG methodology has been implemented on industrial designs. Speed binning has been done on many devices and silicon data has shown significant benefit of the KLPG test, compared to several traditional delay test approaches.
Book Synopsis Statistical Delay Fault Coverage Estimation for Synchronous Sequential Circuits by : Lakshminarayana Pappu
Download or read book Statistical Delay Fault Coverage Estimation for Synchronous Sequential Circuits written by Lakshminarayana Pappu and published by . This book was released on 1996 with total page 146 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis Testing of Digital Systems by : N. K. Jha
Download or read book Testing of Digital Systems written by N. K. Jha and published by Cambridge University Press. This book was released on 2003-05-08 with total page 1016 pages. Available in PDF, EPUB and Kindle. Book excerpt: Device testing represents the single largest manufacturing expense in the semiconductor industry, costing over $40 billion a year. The most comprehensive and wide-ranging book of its kind, Testing of Digital Systems covers everything you need to know about this vitally important subject. Starting right from the basics, the authors take the reader through every key area, including detailed treatment of the latest techniques such as system-on-a-chip and IDDQ testing. Written for students and engineers, it is both an excellent senior/graduate level textbook and a valuable reference.
Book Synopsis Nanometer Technology Designs by : Nisar Ahmed
Download or read book Nanometer Technology Designs written by Nisar Ahmed and published by Springer Science & Business Media. This book was released on 2010-02-26 with total page 288 pages. Available in PDF, EPUB and Kindle. Book excerpt: Traditional at-speed test methods cannot guarantee high quality test results as they face many new challenges. Supply noise effects on chip performance, high test pattern volume, small delay defect test pattern generation, high cost of test implementation and application, and utilizing low-cost testers are among these challenges. This book discusses these challenges in detail and proposes new techniques and methodologies to improve the overall quality of the transition fault test.
Book Synopsis Test and Diagnosis for Small-Delay Defects by : Mohammad Tehranipoor
Download or read book Test and Diagnosis for Small-Delay Defects written by Mohammad Tehranipoor and published by Springer Science & Business Media. This book was released on 2011-09-08 with total page 228 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book will introduce new techniques for detecting and diagnosing small-delay defects in integrated circuits. Although this sort of timing defect is commonly found in integrated circuits manufactured with nanometer technology, this will be the first book to introduce effective and scalable methodologies for screening and diagnosing small-delay defects, including important parameters such as process variations, crosstalk, and power supply noise.
Book Synopsis Signal Stabilization Analysis for Timing Verification and Delay Fault Testing by : Mukund Sivaraman
Download or read book Signal Stabilization Analysis for Timing Verification and Delay Fault Testing written by Mukund Sivaraman and published by . This book was released on 1997 with total page 107 pages. Available in PDF, EPUB and Kindle. Book excerpt: Abstract: "Present-day digital systems are characterized by large complexity, operation under tight timing constraints, numerous false paths, and large variations in component delays. In such a scenario, it is very important to ensure correct temporal behavior of these circuits, both before and after fabrication. For combinational circuits, it has been shown that it is necessary and sufficient to guarantee that the primitive path delay faults (primitive PDFs) are fault-free to ensure that the circuit operates correctly for some timing constraint T and all larger timing constraints, where primitive PDFs correspond to minimal sets of paths that are singly/jointly non-robustly testable. We show that primitive PDFs determine the stabilization time of the circuit outputs, based on which we develop a feasible method to identify the primitive PDFs in a general multilevel logic circuit. We also develop an approach to determine the maximum circuit delay using this primitive PDF identification mechanism, and prove that this delay is exactly equal to the maximum circuit delay found under the floating mode of operation assumption. Our timing analysis approach provides several advantages over previously reported floating mode timing analyzers: increased accuracy in the presence of component delay correlations and signal correlations arising from fabrication process, signal propagation, and signal interaction effects; increased efficiency in situations where critical paths need to be re- identified due to component delay speedup (e.g., post-layout delay optimization). We also present a framework for the diagnosis of circuit failures caused by distributed path delay faults. This involves determining the paths/sub-paths and fabrication process parameters that caused the chip failure. A metric to quantify the diagnosability of a path delay fault for a test is also proposed. Finally, we propose a very realistic metric for delay fault coverage which accounts for delay fault size distributions and is applicable to any delay fault model. We apply this metric to estimate the true delay fault coverage of robust test sets."
