Author : Bo Fu
Publisher :
ISBN 13 :
Total Pages : 390 pages
Book Rating : 4.:/5 (66 download)
Book Synopsis Crosstalk-aware Multiple Error Control for Reliable On-chip Interconnects by : Bo Fu
Download or read book Crosstalk-aware Multiple Error Control for Reliable On-chip Interconnects written by Bo Fu and published by . This book was released on 2010 with total page 390 pages. Available in PDF, EPUB and Kindle. Book excerpt: "To achieve high speed, energy efficient and reliable on-chip communication, solutions that can simultaneously address multiple logic errors and crosstalk-induced delay uncertainty are needed. In this dissertation, we propose a method for combining Hamming product codes and type-II hybrid automatic repeat request (HARQ) with skewed transitions to address this critical issue. As technology scales, interconnects are becoming susceptible to multiple random and burst errors, requiring more powerful error control coding (ECC) techniques than those previously used. We propose the combination of Hamming product codes with type-II HARQ to provide a strong yet energy-efficient error control approach for onchip interconnects. We analyze the performance of the proposed method in terms of the required number of wires, codec delay and residual flit error rate. The proposed method is shown to achieve several orders of magnitude reduction in residual flit error rate compared to previous solutions when multiple random and burst errors are considered. Two design scenarios are investigated. For implementation with low link swing voltages, the combination of Hamming product codes with type-II HARQ are shown to meet the same reliability requirements as previous solutions while using a lower link swing voltage, reducing energy consumption. The proposed method can also be integrated into a configurable error control approach by combining it with a traditional Hamming code. The different coding strengths provided by this realization can achieve better energy performance in the presence of varying noise conditions. Further, the inherent skew resulting from the ECC parity generation is exploited to ensure that no two adjacent wires switch in opposite directions simultaneously, thereby reducing worst-case on-chip capacitive coupling. Instead of waiting for the parity computation to send the original input data and parity bits to the link at the same time, we send the original input data before the parity bits are available. A mapping algorithm is proposed to properly map data and parity check bits to link driver registers, which are triggered by alternating clock phases. The proposed method hides the delay insertion overhead of conventional skewed transition methods. Compared to other solutions that simultaneously handle logic errors and delay uncertainty, the proposed method requires fewer wires, resulting in smaller link area and energy consumption"--leaves iv-v.
