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A Low Power Low Area 10 Bit Sar Adc With Length Based Capacitive Dac
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Book Synopsis A Low-power, Low-area 10-bit SAR ADC with Length-based Capacitive DAC by : Zhili Pan
Download or read book A Low-power, Low-area 10-bit SAR ADC with Length-based Capacitive DAC written by Zhili Pan and published by . This book was released on 2022 with total page 0 pages. Available in PDF, EPUB and Kindle. Book excerpt: A 2.5 V single-ended 10-bit successive-approximation-register analog-to-digital converter (SAR ADC) based on the TSMC 65 nm CMOS process is designed with the goal of achieving low power consumption (33.63 pJ/sample) and small area (2874 μm2 ). It utilizes a novel length-based capacitive digital-to-analog converter (CDAC) layout to achieve low total capacitance for power efficiency, and a custom static asynchronous logic to free the dependence on a high-frequency external clock source. Two test chips have been designed and the problems found through testing the first chip are analyzed. Multiple improved versions of the ADC with minor variations are implemented on the second test chip for performance evaluation, and the test method is explained.
Book Synopsis Low-Power High-Speed ADCs for Nanometer CMOS Integration by : Zhiheng Cao
Download or read book Low-Power High-Speed ADCs for Nanometer CMOS Integration written by Zhiheng Cao and published by Springer Science & Business Media. This book was released on 2008-07-15 with total page 95 pages. Available in PDF, EPUB and Kindle. Book excerpt: Low-Power High-Speed ADCs for Nanometer CMOS Integration is about the design and implementation of ADC in nanometer CMOS processes that achieve lower power consumption for a given speed and resolution than previous designs, through architectural and circuit innovations that take advantage of unique features of nanometer CMOS processes. A phase lock loop (PLL) clock multiplier has also been designed using new circuit techniques and successfully tested. 1) A 1.2V, 52mW, 210MS/s 10-bit two-step ADC in 130nm CMOS occupying 0.38mm2. Using offset canceling comparators and capacitor networks implemented with small value interconnect capacitors to replace resistor ladder/multiplexer in conventional sub-ranging ADCs, it achieves 74dB SFDR for 10MHz and 71dB SFDR for 100MHz input. 2) A 32mW, 1.25GS/s 6-bit ADC with 2.5GHz internal clock in 130nm CMOS. A new type of architecture that combines flash and SAR enables the lowest power consumption, 6-bit >1GS/s ADC reported to date. This design can be a drop-in replacement for existing flash ADCs since it does require any post-processing or calibration step and has the same latency as flash. 3) A 0.4ps-rms-jitter (integrated from 3kHz to 300MHz offset for >2.5GHz) 1-3GHz tunable, phase-noise programmable clock-multiplier PLL for generating sampling clock to the SAR ADC. A new loop filter structure enables phase error preamplification to lower PLL in-band noise without increasing loop filter capacitor size.
Book Synopsis Charge-Sharing SAR ADCs for Low-Voltage Low-Power Applications by : Taimur Rabuske
Download or read book Charge-Sharing SAR ADCs for Low-Voltage Low-Power Applications written by Taimur Rabuske and published by Springer. This book was released on 2016-08-02 with total page 173 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book introduces readers to the potential of charge-sharing (CS) successive approximation register (SAR) analog-to-digital converters (ADCs), while providing extensive analysis of the factors that limit the performance of the CS topology. The authors present guidelines and useful techniques for mitigating the limitations of the architecture, while focusing on the implementation under restricted power budgets and voltage supplies.
Book Synopsis Design and Implementation of Radix-3/Radix-2 Based Novel Hybrid SAR ADC in Scaled CMOS Technologies by : Md. Manzur Rahman
Download or read book Design and Implementation of Radix-3/Radix-2 Based Novel Hybrid SAR ADC in Scaled CMOS Technologies written by Md. Manzur Rahman and published by . This book was released on 2017 with total page 292 pages. Available in PDF, EPUB and Kindle. Book excerpt: This thesis focuses on low power and high speed design techniques for successive approximation register (SAR) analog-to-digital converters (ADCs) in nanoscale CMOS technologies. SAR ADCs’ speed is limited by the number of bits of resolution. An N-bit conventional SAR ADC takes N conversion cycles. To speed up the conversion process, we introduce a radix-3 SAR ADC which can compute 1:6 bits per cycle. To our knowledge, it is the first fully programmable and efficiently hardware controlled radix-3 SAR ADC. We had to use two comparators per cycle due to ADC architecture and we proposed a simple calibration scheme for the comparators. Also, as the architecture of the DAC array is completely different from the architecture of conventional radix-2 SAR ADC’s DAC arrays, we came up with an algorithm for calibration of capacitors of the DAC. Low power SAR ADCs face two major challenges especially at high resolutions: (1) increased comparator power to suppress the noise, and (2) increased DAC switching energy due to the large DAC size. Due to our proposed architecture,the radix-3 SAR ADC uses two comparators per cycle and two differential DACs. To improve the comparator’s power efficiency, an efficient and low cost calibration technique has been introduced. It allows a low power and noisy comparator to achieve high signal-to-noise ratio (SNR). To improve the DAC switching energy, we introduced a radix-3/radix-2 based novel hybrid SAR ADC. We use two single ended DACs for radix-3 SAR ADC and these two single ended DACs can be used as one differential DAC for radix-2 SAR ADC. So, overall, we only have a single DAC as conventional radix- 2 SAR ADC. In addition, a monotonic switching technique is adopted for radix-2 search to reduce the DAC capacitor size and hence, to reduce switching power. It can reduce the total number of unit capacitors by four times. Our proposed hybrid SAR ADC can achieve less DAC energy compared to radix-3 and radix-2 SAR ADCs. Also, to utilize technology scaling, we used the minimum capacitor size allowed by thermal noise limitations. To achieve high resolution, we introduced calibration algorithm for the DAC array. As mentioned earlier, the radix-3 SAR ADC offers higher power than conventional radix-2 SAR ADC because of simultaneous use of two comparators. In the proposed hybrid SAR ADC, we will be using radix-3 search for first few MSB bits. So, the resolution required for radix-3 comparators are much larger than the LSB value of 10-bit ADC. By implementing calibration of comparators, we can use low power, high input referred offset and high speed comparators for radix-3 search. Radix-2 search will be used for rest of the bits and the resolution of the radix-2 comparator has to be less than the required LSB value. So, a high power, low input referred offset and high speed comparator is used for radix-2 search. Also, we introduced clock gating for comparators. So, radix-3 comparators will not toggle during radix-2 search and the radix-2 comparators will be inactive during radix-3 search. By using the aforementioned techniques, the overall comparator power is definitely less than a radix-3 SAR ADC and comparable to a conventional radix-2 SAR ADC. A prototype radix-3/radix-2 based hybrid SAR ADC with the proposed technique is designed and fabricated in 40nm CMOS technology. It achieves an SNDR of 56.9 dB and consumes only 0.38 mW power at 30MS/s, leading to a Walden figure of merit of 21.5 fJ/conv-step.
Book Synopsis Implementation of a 10-bit A-SAR ADC Circuit Based on Voltage to Time Conversion by : Suresh Koyada
Download or read book Implementation of a 10-bit A-SAR ADC Circuit Based on Voltage to Time Conversion written by Suresh Koyada and published by . This book was released on 2016 with total page 176 pages. Available in PDF, EPUB and Kindle. Book excerpt: Comparators are widely used in analog to digital converters. However, the scaling of CMOS technologies makes the design of low power voltage comparators difficult. In order to overcome this problem time-based comparators are introduced which are suitable for nanometer CMOS technology and low supply voltages. This thesis presents the transistor level implementation of a 10-bit time-based accelerated SAR ADC with a supply voltage of 0.5 V. The design increases the conversion speed compared to conventional SAR ADC by updating the upper bound and lower bound of the search space more aggressively. Various design issues, including optimal switch design, glitch minimization at the charge scaling capacitor array output are discussed. This design achieves a SNDR of 58.78dB at a sampling rate of 90.9kS/s and ENOB (effective number of bits) of 9.47 bits with a power consumption of 280nW.
Book Synopsis VLSI, Communication and Signal Processing by : R. K. Nagaria
Download or read book VLSI, Communication and Signal Processing written by R. K. Nagaria and published by Springer Nature. This book was released on 2023-07-01 with total page 867 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book covers a variety of topics in Electronics and Communication Engineering, especially in the area of microelectronics and VLSI design, communication systems and networks, and signal and image processing. The content is based on papers presented at the 5th International Conference on VLSI, Communication and Signal Processing (VCAS 2022). The book also discusses the emerging applications of novel tools and techniques in image, video, and multimedia signal processing. This book is useful to students, researchers, and professionals working in the electronics and communication domain.
Book Synopsis A Low Power 10-Bit SAR ADC with DT-MOS at Ultra-Low Supply Voltage by : 簡豪廷
Download or read book A Low Power 10-Bit SAR ADC with DT-MOS at Ultra-Low Supply Voltage written by 簡豪廷 and published by . This book was released on 2018 with total page 97 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis A Study of SAR ADC and Implementation of 10-bit Asynchronous Design by : Olga Kardonik
Download or read book A Study of SAR ADC and Implementation of 10-bit Asynchronous Design written by Olga Kardonik and published by . This book was released on 2013 with total page 126 pages. Available in PDF, EPUB and Kindle. Book excerpt: Successive Approximation Register (SAR) Analog-to-Digital Converters (ADCs) achieve low power consumption due to its simple architecture based on dominant digital content. SAR ADCs do not require an op-amp, so they are advantageous in CMOS technology scaling. The architecture is often the best choice for battery-powered or mobile applications which need medium resolution (8-12 bits), medium speed (10 - 100 MS/s) and require low-power consumption and small form factor. This work studies the architecture in depth, highlighting its main constraints and tradeoffs involving into SAR ADC design. The work researches asynchronous operation of SAR logic and investigates the latest trends for ADC's analog components - comparator and DAC. 10-bit asynchronous SAR ADC is implemented in CMOS 0.18 μm. Design's noise and power are presented as a breakdown among components.
Book Synopsis Pipelined ADC Design and Enhancement Techniques by : Imran Ahmed
Download or read book Pipelined ADC Design and Enhancement Techniques written by Imran Ahmed and published by Springer Science & Business Media. This book was released on 2010-03-10 with total page 225 pages. Available in PDF, EPUB and Kindle. Book excerpt: Pipelined ADCs have seen phenomenal improvements in performance over the last few years. As such, when designing a pipelined ADC a clear understanding of the design tradeoffs, and state of the art techniques is required to implement today's high performance low power ADCs.
Book Synopsis Data Conversion Handbook by : Walt Kester
Download or read book Data Conversion Handbook written by Walt Kester and published by Newnes. This book was released on 2005 with total page 977 pages. Available in PDF, EPUB and Kindle. Book excerpt: This complete update of a classic handbook originally created by Analog Devices and never previously published offers the most complete and up-to-date reference available on data conversion, from the world authority on the subject. It describes in depth the theory behind and the practical design of data conversion circuits. It describes the different architectures used in A/D and D/A converters - including many advances that have been made in this technology in recent years - and provides guidelines on which types are best suited for particular applications. It covers error characterization and testing specifications, essential design information that is difficult to find elsewhere. The book also contains a wealth of practical application circuits for interfacing and supporting A/D and D/A converters within an electronic system. In short, everything an electronics engineer needs to know about data converters can be found in this volume, making it an indispensable reference with broad appeal. The accompanying CD-ROM provides software tools for testing and analyzing data converters as well as a searchable pdf version of the text. * brings together a huge amount of information impossible to locate elsewhere. * many recent advances in converter technology simply aren't covered in any other book. * a must-have design reference for any electronics design engineer or technician
Book Synopsis A 10-bit 100-kS/s Low Power SAR ADC with Time-based Fixed Window by : 何政勳
Download or read book A 10-bit 100-kS/s Low Power SAR ADC with Time-based Fixed Window written by 何政勳 and published by . This book was released on 2012 with total page 97 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis High-Resolution and High-Speed Integrated CMOS AD Converters for Low-Power Applications by : Weitao Li
Download or read book High-Resolution and High-Speed Integrated CMOS AD Converters for Low-Power Applications written by Weitao Li and published by Springer. This book was released on 2017-08-01 with total page 181 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book is a step-by-step tutorial on how to design a low-power, high-resolution (not less than 12 bit), and high-speed (not less than 200 MSps) integrated CMOS analog-to-digital (AD) converter, to respond to the challenge from the rapid growth of IoT. The discussion includes design techniques on both the system level and the circuit block level. In the architecture level, the power-efficient pipelined AD converter, the hybrid AD converter and the time-interleaved AD converter are described. In the circuit block level, the reference voltage buffer, the opamp, the comparator, and the calibration are presented. Readers designing low-power and high-performance AD converters won’t want to miss this invaluable reference. Provides an in-depth introduction to the newest design techniques for the power-efficient, high-resolution (not less than 12 bit), and high-speed (not less than 200 MSps) AD converter; Presents three types of power-efficient architectures of the high-resolution and high-speed AD converter; Discusses the relevant circuit blocks (i.e., the reference voltage buffer, the opamp, and the comparator) in two aspects, relaxing the requirements and improving the performance.
Book Synopsis VLSI Design and Test by : Anirban Sengupta
Download or read book VLSI Design and Test written by Anirban Sengupta and published by Springer. This book was released on 2019-08-17 with total page 775 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book constitutes the refereed proceedings of the 23st International Symposium on VLSI Design and Test, VDAT 2019, held in Indore, India, in July 2019. The 63 full papers were carefully reviewed and selected from 199 submissions. The papers are organized in topical sections named: analog and mixed signal design; computing architecture and security; hardware design and optimization; low power VLSI and memory design; device modelling; and hardware implementation.
Book Synopsis Principles of Data Conversion System Design by : Behzad Razavi
Download or read book Principles of Data Conversion System Design written by Behzad Razavi and published by Wiley-IEEE Press. This book was released on 1995 with total page 280 pages. Available in PDF, EPUB and Kindle. Book excerpt: This advanced text and reference covers the design and implementation of integrated circuits for analog-to-digital and digital-to-analog conversion. It begins with basic concepts and systematically leads the reader to advanced topics, describing design issues and techniques at both circuit and system level. Gain a system-level perspective of data conversion units and their trade-offs with this state-of-the art book. Topics covered include: sampling circuits and architectures, D/A and A/D architectures; comparator and op amp design; calibration techniques; testing and characterization; and more!
Book Synopsis Next-Generation ADCs, High-Performance Power Management, and Technology Considerations for Advanced Integrated Circuits by : Andrea Baschirotto
Download or read book Next-Generation ADCs, High-Performance Power Management, and Technology Considerations for Advanced Integrated Circuits written by Andrea Baschirotto and published by Springer Nature. This book was released on 2019-10-24 with total page 324 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book is based on the 18 tutorials presented during the 28th workshop on Advances in Analog Circuit Design. Expert designers present readers with information about a variety of topics at the frontier of analog circuit design, including next-generation analog-to-digital converters , high-performance power management systems and technology considerations for advanced IC design. For anyone involved in analog circuit research and development, this book will be a valuable summary of the state-of-the-art in these areas. Provides a summary of the state-of-the-art in analog circuit design, written by experts from industry and academia; Presents material in a tutorial-based format; Includes coverage of next-generation analog-to-digital converters, high-performance power management systems, and technology considerations for advanced IC design.
Book Synopsis Design Techniques for Low Power High Speed Successive Approximation Analog-to-digital Converters by : Jiaming Lin
Download or read book Design Techniques for Low Power High Speed Successive Approximation Analog-to-digital Converters written by Jiaming Lin and published by . This book was released on 2013 with total page 75 pages. Available in PDF, EPUB and Kindle. Book excerpt: This dissertation presents two high-speed pipeline successive approximation analog-to-digital converters (SAR ADCs). Capacitive DACs and resistive DACs are utilized in these two pipeline SAR ADCs, respectively. The pipeline SAR ADC with capacitive DACs can save 50% switching power compared with other time-interleaved SAR ADCs since the total capacitance of the DACs in this ADC is more than 50% less than the conventional time-interleave ones. Several switching techniques are implemented to alleviate the impact from the parasitic capacitance and improve the performance. The pipeline SAR ADC with resistive DACs overcomes the influence from the parasitic capacitance with negligible static power consumption on the resistive DACs. Also, the complicated switching techniques can be avoided to simplify the timing logic. To verify the above two architectures, two chips were designed and fabricated in 40nm CMOS process. Finally, a new architecture of multi-step capacitive-splitting SAR ADC is proposed for low power applications. By using two identical capacitor-splitting capacitor arrays, the switching power and capacitor area can be reduced significantly.
Book Synopsis A 10-bit 27-MS/s Low Power SAR ADC by : 楊孟法
Download or read book A 10-bit 27-MS/s Low Power SAR ADC written by 楊孟法 and published by . This book was released on 2010 with total page 144 pages. Available in PDF, EPUB and Kindle. Book excerpt:
