Microstructure And Processing Effects On Stress And Reliability For Through Silicon Vias Tsvs In 3d Integrated Circuits

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Microstructure and Processing Effects on Stress and Reliability for Through-silicon Vias (TSVs) in 3D Integrated Circuits

Author : Tengfei Jiang
Publisher :
ISBN 13 :
Total Pages : 320 pages
Book Rating : 4.:/5 (983 download)

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Book Synopsis Microstructure and Processing Effects on Stress and Reliability for Through-silicon Vias (TSVs) in 3D Integrated Circuits by : Tengfei Jiang

Download or read book Microstructure and Processing Effects on Stress and Reliability for Through-silicon Vias (TSVs) in 3D Integrated Circuits written by Tengfei Jiang and published by . This book was released on 2015 with total page 320 pages. Available in PDF, EPUB and Kindle. Book excerpt: Copper (Cu) Through-silicon via (TSV) is a key enabling element that provides the vertical connection between stacked dies in three-dimensional (3D) integration. The thermal expansion mismatch between Cu and Si induces complex stresses in and around the TSV structures, which can degrade the performance and reliability of 3DICs and are key concerns for technology development. In this dissertation, the effects of Cu microstructure and processing conditions on the stress characteristics and reliability of the TSV structure are studied. First, the stress characteristics of Cu TSV structures are investigated using the substrate curvature method. The substrate curvature measurement was supplemented by microstructure and finite element analyses (FEA) to investigate the mechanisms for the linear and nonlinear stress-temperature behaviors observed for the TSV structure. Implications of the near surface stress on carrier mobility change and device keep-out zone (KOZ) are discussed. Second, via extrusion, an important yield and reliability issue for 3D integration, is analyzed. Synchrotron x-ray microdiffraction technique was introduced for direct measurements of local stress and material behaviors in and around the TSV. Local plasticity near the top of the via was observed which provided direct experimental evidence to support the plasticity mechanism of via extrusion. An analytical model and FEA were used to analyze via extrusion based on local plasticity. Next, the effect of Cu microstructure effect on the thermomechanical behaviors of TSVs is investigated. The contribution from grain boundary and interfacial diffusion on via extrusion and the relaxation mechanisms are discussed. Potential approaches to minimize via extrusion are proposed. Finally, the stress characteristics of 3D die stack structures are studied using synchrotron x-ray microdiffraction. High resolution stress mappings were performed and verified by finite element analysis (FEA). FEA was further developed to estimate the stress effect on device mobility changes and the warpage of the integrated structure.

Stress Management for 3D ICS Using Through Silicon Vias:

Author : Ehrenfried Zschech
Publisher : American Institute of Physics
ISBN 13 : 9780735409385
Total Pages : 0 pages
Book Rating : 4.4/5 (93 download)

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Book Synopsis Stress Management for 3D ICS Using Through Silicon Vias: by : Ehrenfried Zschech

Download or read book Stress Management for 3D ICS Using Through Silicon Vias: written by Ehrenfried Zschech and published by American Institute of Physics. This book was released on 2011-11-23 with total page 0 pages. Available in PDF, EPUB and Kindle. Book excerpt: Scientist and engineers as well as graduate students in the fields of This conference will be of interest to anyone involved in Physics, Electrical Engineering, Materials Science and Engineering, Reliability and Quality Management, both in industry and academia. One current challenge to micro- and nanoelectronics is the understanding of stress-related phenomena in 3D IC integration. Stresses arising in 3D TSV interconnects and in the surrounding materials due to thermal mismatch, microstructure changes or process integration can lead to performance reduction, reliability-limiting degradation and failure of microelectronic products. Understanding stress-related phenomena in new materials used for 3D integration and packaging, particularly using through silicon vias and microbumps, is critical for future microelectronic products. Management of mechanical stress is one of the key enablers for the successful implementation of 3D-integrated circuits using through silicon vias (TSVs). The potential stress-related impact of the 3D integration process on the device characteristics must be understood and shared, and designers need a solution for managing stress. The Proceedings summarize new research results and advances in basic understanding of stress-induced phenomena in 3D IC integration. Modelling and simulation capabilities as well as materials characterization are demonstrated to evaluate the effect of stress on product performance.

The Scaling and Microstructure Effects on the Thermal Stress and Reliability of Through-silicon Vias in 3D Integrated Circuits

Author : Laura Emilie Spinella
Publisher :
ISBN 13 :
Total Pages : 230 pages
Book Rating : 4.:/5 (99 download)

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Book Synopsis The Scaling and Microstructure Effects on the Thermal Stress and Reliability of Through-silicon Vias in 3D Integrated Circuits by : Laura Emilie Spinella

Download or read book The Scaling and Microstructure Effects on the Thermal Stress and Reliability of Through-silicon Vias in 3D Integrated Circuits written by Laura Emilie Spinella and published by . This book was released on 2017 with total page 230 pages. Available in PDF, EPUB and Kindle. Book excerpt: Through-silicon vias (TSVs) enable full three-dimensional integration by providing high-density vertical interconnections, improving device bandwidth and power consumption. However, TSVs pose reliability risks due to the thermal stresses induced by the thermal expansion coefficient mismatch between silicon and copper, which causes thermal stress buildup and TSV extrusion to degrade device reliability and performance. It has been proposed that optimal post-plating annealing or downscaling TSVs could mitigate deleterious effects for TSVs. While results show some reductions in the average extrusion, the worst cases and statistical spread are not improved. This work investigates the scaling and microstructure effects on stress and extrusion statistics of TSVs to assess reliability risks for future 3D technology with continued TSV downscaling. The basic mechanisms of the extrusion phenomenon and its correlation to the copper microstructural characteristics are examined in order to trace the root cause of the high statistical spreads in the extrusion results. Experimental results first establish the characterization of the TSV samples and demonstrate that neither annealing nor downscaling can fully resolve the reliability threats, as further annealing perpetuates abnormal grain growth to increase the TSV extrusion heights and statistical spreads. Extrusion is shown to be statistical in nature, depending on the microstructure and elastic anisotropy of copper, and is not improved by scaling. Synchrotron x-ray microdiffraction is used to measure the local plasticity of individual copper grains and the results were consistent with the extrusion characteristics, confirming the local plasticity mechanism of extrusion. This directly correlates the extrusion profile to the plasticity in the copper grains, where the statistical spread increases with downscaling. Thermomechanical models validate the non-uniform effect of the grain structure on the stress and extrusion behavior. Additionally, a microstructure simulation was carried out, which accounted for the orientation-dependence of the surface, grain boundary, and strain energies. The results, which confirm the statistical scatter observed in the microstructure and extrusion, indicate that elastic anisotropy drives microstructure evolution, causing the bimodal grain distribution upon annealing. The simulation, having been experimentally validated, is further used to assess the scaling effect on copper TSV reliability and the use of alternative materials to improve reliability.

Arbitrary Modeling of TSVs for 3D Integrated Circuits

Author : Khaled Salah
Publisher : Springer
ISBN 13 : 3319076116
Total Pages : 181 pages
Book Rating : 4.3/5 (19 download)

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Book Synopsis Arbitrary Modeling of TSVs for 3D Integrated Circuits by : Khaled Salah

Download or read book Arbitrary Modeling of TSVs for 3D Integrated Circuits written by Khaled Salah and published by Springer. This book was released on 2014-08-21 with total page 181 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book presents a wide-band and technology independent, SPICE-compatible RLC model for through-silicon vias (TSVs) in 3D integrated circuits. This model accounts for a variety of effects, including skin effect, depletion capacitance and nearby contact effects. Readers will benefit from in-depth coverage of concepts and technology such as 3D integration, Macro modeling, dimensional analysis and compact modeling, as well as closed form equations for the through silicon via parasitics. Concepts covered are demonstrated by using TSVs in applications such as a spiral inductor and inductive-based communication system and bandpass filtering.

Through-Silicon Vias for 3D Integration

Author : John H. Lau
Publisher : McGraw Hill Professional
ISBN 13 : 0071785159
Total Pages : 513 pages
Book Rating : 4.0/5 (717 download)

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Book Synopsis Through-Silicon Vias for 3D Integration by : John H. Lau

Download or read book Through-Silicon Vias for 3D Integration written by John H. Lau and published by McGraw Hill Professional. This book was released on 2012-08-05 with total page 513 pages. Available in PDF, EPUB and Kindle. Book excerpt: A comprehensive guide to TSV and other enabling technologies for 3D integration Written by an expert with more than 30 years of experience in the electronics industry, Through-Silicon Vias for 3D Integration provides cutting-edge information on TSV, wafer thinning, thin-wafer handling, microbumping and assembly, and thermal management technologies. Applications to highperformance, high-density, low-power-consumption, wide-bandwidth, and small-form-factor electronic products are discussed. This book offers a timely summary of progress in all aspects of this fascinating field for professionals active in 3D integration research and development, those who wish to master 3D integration problem-solving methods, and anyone in need of a low-power, wide-bandwidth design and high-yield manufacturing process for interconnect systems. Coverage includes: Nanotechnology and 3D integration for the semiconductor industry TSV etching, dielectric-, barrier-, and seed-layer deposition, Cu plating, CMP, and Cu revealing TSVs: mechanical, thermal, and electrical behaviors Thin-wafer strength measurement Wafer thinning and thin-wafer handling Microbumping, assembly, and reliability Microbump electromigration Transient liquid-phase bonding: C2C, C2W, and W2W 2.5D IC integration with interposers 3D IC integration with interposers Thermal management of 3D IC integration 3D IC packaging

3D Microelectronic Packaging

Author : Yan Li
Publisher : Springer Nature
ISBN 13 : 9811570906
Total Pages : 629 pages
Book Rating : 4.8/5 (115 download)

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Book Synopsis 3D Microelectronic Packaging by : Yan Li

Download or read book 3D Microelectronic Packaging written by Yan Li and published by Springer Nature. This book was released on 2020-11-23 with total page 629 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book offers a comprehensive reference guide for graduate students and professionals in both academia and industry, covering the fundamentals, architecture, processing details, and applications of 3D microelectronic packaging. It provides readers an in-depth understanding of the latest research and development findings regarding this key industry trend, including TSV, die processing, micro-bumps for LMI and MMI, direct bonding and advanced materials, as well as quality, reliability, fault isolation, and failure analysis for 3D microelectronic packages. Images, tables, and didactic schematics are used to illustrate and elaborate on the concepts discussed. Readers will gain a general grasp of 3D packaging, quality and reliability concerns, and common causes of failure, and will be introduced to developing areas and remaining gaps in 3D packaging that can help inspire future research and development.

Power Electronic Packaging

Author : Yong Liu
Publisher : Springer Science & Business Media
ISBN 13 : 1461410533
Total Pages : 606 pages
Book Rating : 4.4/5 (614 download)

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Book Synopsis Power Electronic Packaging by : Yong Liu

Download or read book Power Electronic Packaging written by Yong Liu and published by Springer Science & Business Media. This book was released on 2012-02-15 with total page 606 pages. Available in PDF, EPUB and Kindle. Book excerpt: Power Electronic Packaging presents an in-depth overview of power electronic packaging design, assembly,reliability and modeling. Since there is a drastic difference between IC fabrication and power electronic packaging, the book systematically introduces typical power electronic packaging design, assembly, reliability and failure analysis and material selection so readers can clearly understand each task's unique characteristics. Power electronic packaging is one of the fastest growing segments in the power electronic industry, due to the rapid growth of power integrated circuit (IC) fabrication, especially for applications like portable, consumer, home, computing and automotive electronics. This book also covers how advances in both semiconductor content and power advanced package design have helped cause advances in power device capability in recent years. The author extrapolates the most recent trends in the book's areas of focus to highlight where further improvement in materials and techniques can drive continued advancements, particularly in thermal management, usability, efficiency, reliability and overall cost of power semiconductor solutions.

Placement for Fast and Reliable Through-silicon-via (TSV) Based 3D-IC Layouts

Author : Krit Athikulwongse
Publisher :
ISBN 13 :
Total Pages : pages
Book Rating : 4.:/5 (844 download)

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Book Synopsis Placement for Fast and Reliable Through-silicon-via (TSV) Based 3D-IC Layouts by : Krit Athikulwongse

Download or read book Placement for Fast and Reliable Through-silicon-via (TSV) Based 3D-IC Layouts written by Krit Athikulwongse and published by . This book was released on 2012 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: The objective of this research is to explore the feasibility of addressing the major performance and reliability problems or issues, such as wirelength, stress-induced carrier mobility variation, temperature, and quality trade-offs, found in three-dimensional integrated circuits (3D ICs) that use through-silicon vias (TSVs) at placement stage. Four main works that support this goal are included. In the first work, wirelength of TSV-based 3D ICs is the main focus. In the second work, stress-induced carrier mobility variation in TSV-based 3D ICs is examined. In the third work, temperature inside TSV-based 3D ICs is investigated. In the final work, the quality trade-offs of TSV-based 3D-IC designs are explored. In the first work, a force-directed, 3D, and gate-level placement algorithm that efficiently handles TSVs is developed. The experiments based on synthesized benchmarks indicate that the developed algorithm helps generate GDSII layouts of 3D-IC designs that are optimized in terms of wirelength. In addition, the impact of TSVs on other physical aspects of 3D-IC designs is also studied by analyzing the GDSII layouts. In the second work, the model for carrier mobility variation caused by TSV and STI stresses is developed as well as the timing analysis flow considering the stresses. The impact of TSV and STI stresses on carrier mobility variation and performance of 3D ICs is studied. Furthermore, a TSV-stress-driven, force-directed, and 3D placement algorithm is developed. It exploits carrier mobility variation, caused by stress around TSVs after fabrication, to improve the timing and area objectives during placement. In addition, the impact of keep-out zone (KOZ) around TSVs on stress, carrier mobility variation, area, wirelength, and performance of 3D ICs is studied. In the third work, two temperature-aware global placement algorithms are developed. They exploit die-to-die thermal coupling in 3D ICs to improve temperature during placement. In addition, a framework used to evaluate the results from temperature-aware global placements is developed. The main component of the framework is a GDSII-level thermal analysis that considers all structures inside a TSV-based 3D IC while computing temperature. The developed placers are compared with several state-of-the-art placers published in recent literature. The experimental results indicate that the developed algorithms help improve the temperature of 3D ICs effectively. In the final work, three block-level design styles for TSV-based die-to-wafer bonded 3D ICs are discussed. Several 3D-IC layouts in the three styles are manually designed. The main difference among these layouts is the position of TSVs. Finally, the area, wirelength, timing, power, temperature, and mechanical stress of all layouts are compared to explore the trade-offs of layout quality.

Systems-Level Packaging for Millimeter-Wave Transceivers

Author : Mladen Božanić
Publisher : Springer
ISBN 13 : 3030146901
Total Pages : 277 pages
Book Rating : 4.0/5 (31 download)

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Book Synopsis Systems-Level Packaging for Millimeter-Wave Transceivers by : Mladen Božanić

Download or read book Systems-Level Packaging for Millimeter-Wave Transceivers written by Mladen Božanić and published by Springer. This book was released on 2019-03-26 with total page 277 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book provides a system-level approach to making packaging decisions for millimeter-wave transceivers. In electronics, the packaging forms a bridge between the integrated circuit or individual device and the rest of the electronic system, encompassing all technologies between the two. To be able to make well-founded packaging decisions, researchers need to understand a broad range of aspects, including: concepts of transmission bands, antennas and propagation, integrated and discrete package substrates, materials and technologies, interconnects, passive and active components, as well as the advantages and disadvantages of various packages and packaging approaches, and package-level modeling and simulation. Packaging also needs to be considered in terms of system-level testing, as well as associated testing and production costs, and reducing costs. This peer-reviewed work contributes to the extant scholarly literature by addressing the aforementioned concepts and applying them to the context of the millimeter-wave regime and the unique opportunities that this transmission approach offers.

Designing TSVs for 3D Integrated Circuits

Author : Nauman Khan
Publisher : Springer Science & Business Media
ISBN 13 : 1461455073
Total Pages : 82 pages
Book Rating : 4.4/5 (614 download)

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Book Synopsis Designing TSVs for 3D Integrated Circuits by : Nauman Khan

Download or read book Designing TSVs for 3D Integrated Circuits written by Nauman Khan and published by Springer Science & Business Media. This book was released on 2012-09-23 with total page 82 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book explores the challenges and presents best strategies for designing Through-Silicon Vias (TSVs) for 3D integrated circuits. It describes a novel technique to mitigate TSV-induced noise, the GND Plug, which is superior to others adapted from 2-D planar technologies, such as a backside ground plane and traditional substrate contacts. The book also investigates, in the form of a comparative study, the impact of TSV size and granularity, spacing of C4 connectors, off-chip power delivery network, shared and dedicated TSVs, and coaxial TSVs on the quality of power delivery in 3-D ICs. The authors provide detailed best design practices for designing 3-D power delivery networks. Since TSVs occupy silicon real-estate and impact device density, this book provides four iterative algorithms to minimize the number of TSVs in a power delivery network. Unlike other existing methods, these algorithms can be applied in early design stages when only functional block- level behaviors and a floorplan are available. Finally, the authors explore the use of Carbon Nanotubes for power grid design as a futuristic alternative to Copper.

Silicon Compatible Materials, and Technologies for Advanced Integrated Processes, Circuits and Emerging Applications 5

Author : F. Roozeboom
Publisher : The Electrochemical Society
ISBN 13 : 1607685949
Total Pages : 338 pages
Book Rating : 4.6/5 (76 download)

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Book Synopsis Silicon Compatible Materials, and Technologies for Advanced Integrated Processes, Circuits and Emerging Applications 5 by : F. Roozeboom

Download or read book Silicon Compatible Materials, and Technologies for Advanced Integrated Processes, Circuits and Emerging Applications 5 written by F. Roozeboom and published by The Electrochemical Society. This book was released on 2015 with total page 338 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs

Author : Brandon Noia
Publisher : Springer Science & Business Media
ISBN 13 : 3319023780
Total Pages : 260 pages
Book Rating : 4.3/5 (19 download)

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Book Synopsis Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs by : Brandon Noia

Download or read book Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs written by Brandon Noia and published by Springer Science & Business Media. This book was released on 2013-11-19 with total page 260 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable.

Thermo-mechanical Stress Analysis and Interfacial Reliability for Through-silicon Vias in Three-dimensional Interconnect Structures

Download Thermo-mechanical Stress Analysis and Interfacial Reliability for Through-silicon Vias in Three-dimensional Interconnect Structures PDF Online Free

Author : Suk-Kyu Ryu
Publisher :
ISBN 13 :
Total Pages : 282 pages
Book Rating : 4.:/5 (773 download)

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Book Synopsis Thermo-mechanical Stress Analysis and Interfacial Reliability for Through-silicon Vias in Three-dimensional Interconnect Structures by : Suk-Kyu Ryu

Download or read book Thermo-mechanical Stress Analysis and Interfacial Reliability for Through-silicon Vias in Three-dimensional Interconnect Structures written by Suk-Kyu Ryu and published by . This book was released on 2011 with total page 282 pages. Available in PDF, EPUB and Kindle. Book excerpt: Continual scaling of devices and on-chip wiring has brought significant challenges for materials and processes beyond the 32-nm technology node in microelectronics. Recently, three-dimensional (3-D) integration with through-silicon vias (TSVs) has emerged as an effective solution to meet the future interconnect requirements. Among others, thermo-mechanical reliability is a key concern for the development of TSV structures used in die stacking as 3-D interconnects. In this dissertation, thermal stresses and interfacial reliability of TSV structures are analyzed by combining analytical and numerical models with experimental measurements. First, three-dimensional near-surface stress distribution is analyzed for a simplified TSV structure consisting of a single via embedded in a silicon (Si) wafer. A semi-analytic solution is developed and compared with finite element analysis (FEA). For further study, the effects of anisotropic elasticity in Si and metal plasticity in the via on the stress distribution and deformation are investigated. Next, by micro-Raman spectroscopy and bending beam technique, experimental measurements of the thermal stresses in TSV structures are conducted. The micro-Raman measurements characterize the local distribution of the near-surface stresses in Si around TSVs. On the other hand, the bending beam technique measures the average stress and viii deformation in the TSV structures. To understand the elastic and plastic behavior of TSVs, the microstructural evolution of the Cu vias is analyzed using focused ion beam (FIB) and electron backscattering diffraction (EBSD) techniques. To study the impacts of the thermal stresses on interfacial reliability of TSV structures, an analytical solution is developed for the steady-state energy release rate as the upper bound of the driving force for interfacial delamination. The effect of crack length and wafer thickness on the energy release rate is studied by FEA. Furthermore, to model interfacial crack nucleation, an analytical approach is developed by combining a shear lag model with a cohesive interface model. Finally, the effects of structural designs and the variation of the constituent materials on TSV reliability are investigated. The steady state solutions for the energy release rate are developed for various TSV designs and via materials (Al, Cu, Ni, and W) to evaluate the interfacial reliability. The parameters for TSV design optimization are discussed from the perspectives of interfacial reliability.

Stress-Induced Phenomena in Metallization

Author : Ehrenfried Zschech
Publisher : American Inst. of Physics
ISBN 13 : 9780735408555
Total Pages : 0 pages
Book Rating : 4.4/5 (85 download)

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Book Synopsis Stress-Induced Phenomena in Metallization by : Ehrenfried Zschech

Download or read book Stress-Induced Phenomena in Metallization written by Ehrenfried Zschech and published by American Inst. of Physics. This book was released on 2010-12-20 with total page 0 pages. Available in PDF, EPUB and Kindle. Book excerpt: One current challenge to micro- and nanoelectronics is the understanding of stress-related phenomena in metallization. Stresses arising in on-chip and 3D metal interconnects and in the surrounding materials due to thermal mismatch, microstructure changes or process integration as well as electromigration can lead to degradation and failure of microelectronic products. The implementation of low dielectric constant materials into the inlaid copper backend-of-line process has brought new challenges for process integration and reliability. Understanding stress-related phenomena in new materials used for 3D integration and packaging, particularly using through silicon vias and microbumps, is critical for future microelectronic products. The Proceedings summarize new research results and advances in basic understanding of stress-induced phenomena in metallization. In addition to experimental studies, modelling and simulation capabilities are demonstrated to evaluate the effect of stress on product performance and reliability. Stress-related phenomena in 3D IC interconnects are covered too.

Thermo-mechanical Reliability of 3-D Interconnects Containing Through-silicon-vias (TSVs)

Author : Kuan Hsun Lu
Publisher :
ISBN 13 :
Total Pages : 250 pages
Book Rating : 4.:/5 (7 download)

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Book Synopsis Thermo-mechanical Reliability of 3-D Interconnects Containing Through-silicon-vias (TSVs) by : Kuan Hsun Lu

Download or read book Thermo-mechanical Reliability of 3-D Interconnects Containing Through-silicon-vias (TSVs) written by Kuan Hsun Lu and published by . This book was released on 2010 with total page 250 pages. Available in PDF, EPUB and Kindle. Book excerpt: This dissertation focuses on one of the most active research areas in the microelectronics industry: Thermo-mechanical reliability of 3-D interconnects containing through-silicon-vias (TSVs). This study constitutes two parts: 1. Thermal stress measurement on TSVs; 2. Analyses on thermo-mechanical reliability of TSVs. In the first part, a metrology for stress measurement of through-silicon-via (TSV) structures was developed using a bending beam technique. The bending curvature induced by the thermal expansion of a periodic array of Cu TSVs was measured during thermal cycles. The stress components in TSV structures were deduced combining the curvature measurement with a finite-element-analysis (FEA). Temperature-dependent thermal stresses in Cu TSVs and in Si matrix were derived. In the second part, the reliability issues induced by the thermal stresses of TSVs were analyzed from several aspects, including the carrier mobility change in transistors, the interfacial delamination of TSVs, and thermal stress interactions between TSVs. Among them, the mobility change in transistors was found to be sensitive to the normal stresses near the Si wafer surface. The surface area of a high mobility change was defined as the keep-out zone (KOZ) for transistors. FEA simulations were carried out to calculate the area of KOZ surrounding TSVs. The area of KOZ was found to be mainly determined by the channel direction of the transistor as a result of anisotropic piezoresistivity effects. FEA simulations also showed that the KOZ can be controlled by TSV geometry, material selection, etc. Interfacial delamination of TSVs was found to be mainly driven by a shear stress concentration at the TSV/Si interface. Crack driving force for TSV delamination was calculated using FEA simulations, which take into account the magnitude of thermal load, TSV geometry, TSV materials, etc. The results provided a design guideline to improve the TSV delamination problem. In the last, the stress interaction among TSV arrays was examined using a bi-TSV model. In the Cartesian coordinate system, thermal stresses can be intensified or suppressed between TSVs, depending on how TSVs are located. Further analyses suggested that the area of KOZ and the TSV-induced Si cracking can both be improved by optimizing the arrangement of the TSV arrays.

Processing Effect on Via Extrusion for Through-Silicon Vias (TSVs) in 3D Interconnects: A Comparative Study of Two TSV Structures

Author : Tengfei Jiang
Publisher :
ISBN 13 :
Total Pages : pages
Book Rating : 4.:/5 (119 download)

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Book Synopsis Processing Effect on Via Extrusion for Through-Silicon Vias (TSVs) in 3D Interconnects: A Comparative Study of Two TSV Structures by : Tengfei Jiang

Download or read book Processing Effect on Via Extrusion for Through-Silicon Vias (TSVs) in 3D Interconnects: A Comparative Study of Two TSV Structures written by Tengfei Jiang and published by . This book was released on 2016 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt:

Thermo-mechanical Reliability of Micro-interconnects in Three-dimensional Integrated Circuits

Author : Omar Rodriguez
Publisher :
ISBN 13 :
Total Pages : 75 pages
Book Rating : 4.:/5 (662 download)

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Book Synopsis Thermo-mechanical Reliability of Micro-interconnects in Three-dimensional Integrated Circuits by : Omar Rodriguez

Download or read book Thermo-mechanical Reliability of Micro-interconnects in Three-dimensional Integrated Circuits written by Omar Rodriguez and published by . This book was released on 2010 with total page 75 pages. Available in PDF, EPUB and Kindle. Book excerpt: Three-dimensional integrated circuits (3D ICs) have been designed with the purpose of achieving higher communication speed by reducing the interconnect length between integrated circuits, and integrating heterogeneous functions into one single package, among other advantages. As a growing, new technology, researchers are still studying the different parameters that impact the overall lifetime of such packages in order to ensure the customer receives reliable end products. This study focused on the effect of four design parameters on the lifetime of the interconnects and, in particular, solder balls and through-silicon vias (TSVs). These parameters included TSV pitch, TSV diameter, underfill stiffness and underfill thickness. A three-dimensional finite element model of a 3D IC package was built in ANSYS to analyze the effect of these parameters under thermo-mechanical cyclic loading. The stresses and damage in the interconnects of the IC were evaluated using Coffin-Manson and the energy partitioning fatigue damage models. A three-level Taguchi design of experiment method was utilized to evaluate the effect of each parameter. Minitab software was used to assess the main effects of the selected design parameters. Locations of maximum stresses and possible damage initiation were discussed, and recommendations were made to the manufacturer for package optimization. Due to the very small scale of the interconnects, conducting mechanical tests and measuring strains in small microscopic scale material is very complicated and challenging; therefore, it is very difficult to validate finite element and analytical analysis of stress and strain in microelectronic devices. At the next step of this work, a new device and method were proposed to facilitate testing and strain measurements of material at microscopic scale. This new micro-electromechanical system (MEMS) consisted of two piezoelectric members that were constrained by a rigid frame and that sandwiched the test material. These two piezoelectric members act as load cell and strain measurement sensors. As the voltage is applied to the first member, it induces a force to the specimen and deforms it, which in turn deforms the second piezoelectric member. The second piezoelectric member induces an output voltage that is proportional to its deformation. Therefore, the strain and stresses in the test material can be determined by knowing the mechanical characteristics of the piezoelectric members. Advantages of the proposed system include ease of use, particularly at microscopic scale, adaptability to measure the strain of different materials, and flexibility to measure the modulus of elasticity for an unknown material. An analytical analysis of the device and method was presented, and the finite element simulation of the device was accomplished. The results were compared and discussed. An inelastic specimen was also analyzed and sensitivity of the device to detecting nonlinear behavior was evaluated. A characteristic curve was developed for the specific geometry and piezoelectric material.