Author : Martin Krämer
Publisher :
ISBN 13 :
Total Pages : pages
Book Rating : 4.:/5 (919 download)
Book Synopsis High-resolution SAR A/D Converters with Loop-embedded Input Buffer by : Martin Krämer
Download or read book High-resolution SAR A/D Converters with Loop-embedded Input Buffer written by Martin Krämer and published by . This book was released on 2015 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: Successive-approximation-register (SAR) analog-to-digital converters (ADCs) have generated a significant amount of interest in the past several years. While most of the recent literature focuses on low-to-moderate resolution designs (8-10 bits), we are now beginning to see significant advancements in the high-resolution space, targeting ≥14 bits at 10-100 MS/s. Traditionally, this performance range has been dominated by pipelined and delta-sigma architectures. However, several applications in high-speed control and interference cancellation require low laten-cy and this is where the SAR topology becomes attractive. While several SAR ADCs have demonstrated efficient digitization at high speed and resolution, the difficulty of driving a large sampling capacitor with high accuracy in a short sam-pling window is an important challenge in the System-on-a-Chip (SoC) integration of such ADCs that is often ignored in the literature. The work of this dissertation led to the design of a 14-bit 35 MS/s SAR ADC in 40 nm CMOS with a loop-embedded input buffer that consumes only 23% of the total ADC power. The buffer uses a source follower topology whose nonline-arities are cancelled by the SAR algorithm, allowing us to achieve 99 dB spurious-free dynamic range (SFDR) despite the small amount of invested power. That approach made it possible to reduce the input capacitance of the ADC by a factor of eighteen, easing the drive requirements substantially and resulting in the highest reported SFDR for SAR ADCs with a sampling speed greater than 20 MS/s. Additionally, a second SAR ADC design (30 MS/s) based on a noise filter gear-shifting concept is introduced. Using a comparator with time varying noise performance, this ADC achieves a state-of-the-art figure of merit (FOM) of 161.6 dB and a peak signal to noise-plus-distortion ratio (SNDR) of 77 dB, which is the highest reported value for SAR ADCs with a sampling frequency above 20 MHz.
