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Computation Of Delay Defect And Delay Fault Probabilities Using A Statistical Timing Simulator
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Book Synopsis Computation of Delay Defect and Delay Fault Probabilities Using a Statistical Timing Simulator by : Jacques Benkoski
Download or read book Computation of Delay Defect and Delay Fault Probabilities Using a Statistical Timing Simulator written by Jacques Benkoski and published by . This book was released on 1990 with total page 16 pages. Available in PDF, EPUB and Kindle. Book excerpt: Abstract: "A new approach to computing the delay defect and delay fault probabilities has been developed. Using a formal modeling of the signal interactions, a statistical timing simulator capable of detecting delay faults and computing delay defect distributions has been built. This tool produces the delay fault statistics which must be used by delay fault ATPG tools if they are to realistically model process-induced delay failures."
Book Synopsis Fault Simulation and Test Generation for Small Delay Faults by : Wangqi Qiu
Download or read book Fault Simulation and Test Generation for Small Delay Faults written by Wangqi Qiu and published by . This book was released on 2006 with total page 130 pages. Available in PDF, EPUB and Kindle. Book excerpt: The ATPG methodology has been implemented on industrial designs. Speed binning has been done on many devices and silicon data has shown significant benefit of the KLPG test, compared to several traditional delay test approaches.
Download or read book Proceedings written by and published by . This book was released on 1989 with total page 1012 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis Statistical Timing Verification and Delay Fault Detection by Formal Signal Interaction Modeling in a Multi-level Timing Simulator by : Jacques Benkoski
Download or read book Statistical Timing Verification and Delay Fault Detection by Formal Signal Interaction Modeling in a Multi-level Timing Simulator written by Jacques Benkoski and published by . This book was released on 1989 with total page 90 pages. Available in PDF, EPUB and Kindle. Book excerpt: Abstract: "Modern VLSI designs are characterized by tight timing constraints, increased importance of the parasitics and large correlated variations in the process-dependent parameters. This work is focused on the development of new techniques to verify the timing behavior of the circuit under these process-dependent parameter variations and predict the location and size of the possible delay faults. The formal modeling of signal interaction presented in this thesis has allowed the formulation of conservative conditions on the validity of circuit macromodels. These conditions form the basis of efficient and accurate algorithms for multi-level simulation including dynamic level selection, fast statistical timing simulation and delay fault detection."
Book Synopsis Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits by : Sandeep K. Goel
Download or read book Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits written by Sandeep K. Goel and published by CRC Press. This book was released on 2013-10-25 with total page 266 pages. Available in PDF, EPUB and Kindle. Book excerpt: Advances in design methods and process technologies have resulted in a continuous increase in the complexity of integrated circuits (ICs). However, the increased complexity and nanometer-size features of modern ICs make them susceptible to manufacturing defects, as well as performance and quality issues. Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits covers common problems in areas such as process variations, power supply noise, crosstalk, resistive opens/bridges, and design-for-manufacturing (DfM)-related rule violations. The book also addresses testing for small-delay defects (SDDs), which can cause immediate timing failures on both critical and non-critical paths in the circuit. Overviews semiconductor industry test challenges and the need for SDD testing, including basic concepts and introductory material Describes algorithmic solutions incorporated in commercial tools from Mentor Graphics Reviews SDD testing based on "alternative methods" that explores new metrics, top-off ATPG, and circuit topology-based solutions Highlights the advantages and disadvantages of a diverse set of metrics, and identifies scope for improvement Written from the triple viewpoint of university researchers, EDA tool developers, and chip designers and tool users, this book is the first of its kind to address all aspects of SDD testing from such a diverse perspective. The book is designed as a one-stop reference for current industrial practices, research challenges in the domain of SDD testing, and recent developments in SDD solutions.
Book Synopsis A Unified Approach for Timing Verification and Delay Fault Testing by : Mukund Sivaraman
Download or read book A Unified Approach for Timing Verification and Delay Fault Testing written by Mukund Sivaraman and published by Springer Science & Business Media. This book was released on 2012-09-17 with total page 164 pages. Available in PDF, EPUB and Kindle. Book excerpt: Large system complexities and operation under tight timing constraints in rapidly shrinking technologies have made it extremely important to ensure correct temporal behavior of modern-day digital circuits, both before and after fabrication. Research in (pre-fabrication) timing verification and (post-fabrication) delay fault testing has evolved along largely disjoint lines in spite of the fact that they share many basic concepts. A Unified Approach for Timing Verification and Delay Fault Testing applies concepts developed in the context of delay fault testing to path sensitization, which allows an accurate timing analysis mechanism to be developed. This path sensitization strategy is further applied for efficient delay fault diagnosis and delay fault coverage estimation. A new path sensitization strategy called Signal Stabilization Time Analysis (SSTA) has been developed based on the fact that primitive PDFs determine the stabilization time of the circuit outputs. This analysis has been used to develop a feasible method of identifying the primitive PDFs in a general multi-level logic circuit. An approach to determine the maximum circuit delay using this primitive PDF identification mechanism is also presented. The Primitive PDF Identification-based Timing Analysis (PITA) approach is proved to determine the maximum floating mode circuit delay exactly under any component delay model, and provides several advantages over previously floating mode timing analyzers. A framework for the diagnosis of circuit failures caused by distributed path delay faults is also presented. A metric to quantify the diagnosability of a path delay fault for a test is also proposed. Finally, the book presents a very realistic metric for delay fault coverage which accounts for delay fault size distributions and is applicable to any delay fault model. A Unified Approach for Timing Verification and Delay Fault Testing will be of interest to university and industry researchers in timing analysis and delay fault testing as well as EDA tool development engineers and design verification engineers dealing with timing issues in ULSI circuits. The book should also be of interest to digital designers and others interested in knowing the state of the art in timing verification and delay fault testing.
Download or read book Digest of Papers written by and published by . This book was released on 1997 with total page 138 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis Testing for Delay Defects Utilizing Test Data Compression Techniques by : Richard Dean Putman
Download or read book Testing for Delay Defects Utilizing Test Data Compression Techniques written by Richard Dean Putman and published by . This book was released on 2008 with total page 164 pages. Available in PDF, EPUB and Kindle. Book excerpt: As technology shrinks new types of defects are being discovered and new fault models are being created for those defects. Transition delay and path delay fault models are two such models that have been created, but they still fall short in that they are unable to obtain a high test coverage of smaller delay defects; these defects can cause functional behavior to fail and also indicate potential reliability issues. The first part of this dissertation addresses these problems by presenting an enhanced timing-based delay fault testing technique that incorporates the use of standard delay ATPG, along with timing information gathered from standard static timing analysis. Utilizing delay fault patterns typically increases the test data volume by 3-5X when compared to stuck-at patterns. Combined with the increase in test data volume associated with the increase in gate count that typically accompanies the miniaturization of technology, this adds up to a very large increase in test data volume that directly affect test time and thus the manufacturing cost. The second part of this dissertation presents a technique for improving test compression and reducing test data volume by using multiple expansion ratios while determining the configuration of the scan chains for each of the expansion ratios using a dependency analysis procedure that accounts for structural dependencies as well as free variable dependencies to improve the probability of detecting faults. Finally, this dissertation addresses the problem of unknown values (X's) in the output response data corrupting the data and degrading the performance of the output response compactor and thus the overall amount of test compression. Four techniques are presented that focus on handling response data with large percentages of X's. The first uses X-canceling MISR architecture that is based on deterministically observing scan cells, and the second is a hybrid approach that combines a simple X-masking scheme with the X-canceling MISR for further gains in test compression. The third and fourth techniques revolve around reiterative LFSR X-masking, which take advantage of LFSR-encoded masks that can be reused for multiple scan slices in novel ways.
Book Synopsis Index to IEEE Publications by : Institute of Electrical and Electronics Engineers
Download or read book Index to IEEE Publications written by Institute of Electrical and Electronics Engineers and published by . This book was released on 1990 with total page 848 pages. Available in PDF, EPUB and Kindle. Book excerpt: Issues for 1973- cover the entire IEEE technical literature.
Book Synopsis Recursive Path Selection by : Jaeyong Chung
Download or read book Recursive Path Selection written by Jaeyong Chung and published by . This book was released on 2008 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: This paper presents a new path selection algorithm for delay fault testing in a statistical timing framework. Existing algorithms which consider correlation between paths use an iterative process for each path or defect and requires a Monte Carlo simulation for each iteration to calculate the conditional faulty probability. The proposed algorithm does not require the iteration process and selects a requested number of paths simultaneously once it performs a statistical timing analysis at the beginning. If selection of k paths is required in a set of paths, it partitions the set into two path sets and determines how many paths should be selected in each path set out of the k paths. It recursively continues this process and ends up with k paths. The partitioning is easily performed during the recursive traversal of a circuit, which produces an imaginary path tree, where paths are already grouped based on their prefix. Experimental results show the proposed algorithm can effectively use structural correlation and spatial correlation to generate high quality path sets.
Book Synopsis Statistical Coverage Estimation for Path Delay Faults by : Mukund Sivaraman
Download or read book Statistical Coverage Estimation for Path Delay Faults written by Mukund Sivaraman and published by . This book was released on 1995 with total page 19 pages. Available in PDF, EPUB and Kindle. Book excerpt: Abstract: "In this paper, we propose a new and realistic definition of path delay fault coverage, based on the percentage of fabricated faulty chips which can be detected as faulty by a given test set. This metric takes into account the probability distribution of fault sizes caused by fabrication process effects. Previously, metrics for the effectiveness of a test set for path delay faults have been based on the percentage of paths tested. Also, gate delay fault test quality and coverage metrics which take into account fault sizes and, in one case [24], fault size distributions, are limited in scope to only single, localized gate delay defects. Moreover, results which show computationally efficient means of estimating gate delay fault coverages using such metrics are lacking. In addition to proposing a realistic delay fault coverage metric, we also present a computationally viable scheme for using this metric to estimate the coverage of any given test set for path delay faults caused by fabrication process variations. We use the results for the ISCAS'89 and Logic synthesis'91 benchmark circuits to demonstrate wide discrepancies between parametric path delay fault coverage estimates for robust test sets obtained using our realistic definition, and the ones obtained by using the traditional notion of coverage as the percentage of paths tested."
Book Synopsis Computational Science – ICCS 2020 by : Valeria V. Krzhizhanovskaya
Download or read book Computational Science – ICCS 2020 written by Valeria V. Krzhizhanovskaya and published by Springer Nature. This book was released on 2020-06-18 with total page 618 pages. Available in PDF, EPUB and Kindle. Book excerpt: The seven-volume set LNCS 12137, 12138, 12139, 12140, 12141, 12142, and 12143 constitutes the proceedings of the 20th International Conference on Computational Science, ICCS 2020, held in Amsterdam, The Netherlands, in June 2020.* The total of 101 papers and 248 workshop papers presented in this book set were carefully reviewed and selected from 719 submissions (230 submissions to the main track and 489 submissions to the workshops). The papers were organized in topical sections named: Part I: ICCS Main Track Part II: ICCS Main Track Part III: Track of Advances in High-Performance Computational Earth Sciences: Applications and Frameworks; Track of Agent-Based Simulations, Adaptive Algorithms and Solvers; Track of Applications of Computational Methods in Artificial Intelligence and Machine Learning; Track of Biomedical and Bioinformatics Challenges for Computer Science Part IV: Track of Classifier Learning from Difficult Data; Track of Complex Social Systems through the Lens of Computational Science; Track of Computational Health; Track of Computational Methods for Emerging Problems in (Dis-)Information Analysis Part V: Track of Computational Optimization, Modelling and Simulation; Track of Computational Science in IoT and Smart Systems; Track of Computer Graphics, Image Processing and Artificial Intelligence Part VI: Track of Data Driven Computational Sciences; Track of Machine Learning and Data Assimilation for Dynamical Systems; Track of Meshfree Methods in Computational Sciences; Track of Multiscale Modelling and Simulation; Track of Quantum Computing Workshop Part VII: Track of Simulations of Flow and Transport: Modeling, Algorithms and Computation; Track of Smart Systems: Bringing Together Computer Vision, Sensor Networks and Machine Learning; Track of Software Engineering for Computational Science; Track of Solving Problems with Uncertainties; Track of Teaching Computational Science; Track of UNcErtainty QUantIficatiOn for ComputationAl modeLs *The conference was canceled due to the COVID-19 pandemic.
Book Synopsis Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation by : Lars Svensson
Download or read book Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation written by Lars Svensson and published by Springer. This book was released on 2009-01-30 with total page 474 pages. Available in PDF, EPUB and Kindle. Book excerpt: Welcome to the proceedings of PATMOS 2008, the 18th in a series of int- national workshops. PATMOS 2008 was organized by INESC-ID / IST - TU Lisbon, Portugal, with sponsorship by Cadence, IBM, Chipidea, and Tecmic, and technical co-sponsorship by the IEEE. Over the years, PATMOS has evolved into an important European event, where researchers from both industry and academia discuss and investigate the emerging challenges in future and contemporary applications, design meth- ologies, and tools required for the development of the upcoming generations of integrated circuits and systems. The technical program of PATMOS 2008 c- tained state-of-the-art technical contributions, three invited talks, and a special session on recon?gurable architectures. The technical program focused on t- ing, performance and power consumption, as well as architectural aspects with particular emphasis on modeling, design, characterization, analysis and op- mization in the nanometer era. The Technical Program Committee, with the assistance of additional expert reviewers, selected the 41 papers presented at PATMOS. The papers were - ganized into 7 oral sessions (with a total of 31 papers) and 2 poster sessions (with a total of 10 papers). As is customary for the PATMOS workshops, full papers were required for review, and a minimum of three reviews were received per manuscript.
Book Synopsis Fault Simulation and Test Pattern Selectionfor Small Delay Defects Using Gpu by : 許聖章
Download or read book Fault Simulation and Test Pattern Selectionfor Small Delay Defects Using Gpu written by 許聖章 and published by . This book was released on 2013 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book IEEE VLSI Test Symposium written by and published by . This book was released on 2003 with total page 474 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Download or read book Digest of Technical Papers written by and published by . This book was released on 1986 with total page 568 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis System-on-Chip Test Architectures by : Laung-Terng Wang
Download or read book System-on-Chip Test Architectures written by Laung-Terng Wang and published by Morgan Kaufmann. This book was released on 2010-07-28 with total page 893 pages. Available in PDF, EPUB and Kindle. Book excerpt: Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today's overall product cost. This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and VLSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs. Emphasizes VLSI Test principles and Design for Testability architectures, with numerous illustrations/examples. Most up-to-date coverage available, including Fault Tolerance, Low-Power Testing, Defect and Error Tolerance, Network-on-Chip (NOC) Testing, Software-Based Self-Testing, FPGA Testing, MEMS Testing, and System-In-Package (SIP) Testing, which are not yet available in any testing book. Covers the entire spectrum of VLSI testing and DFT architectures, from digital and analog, to memory circuits, and fault diagnosis and self-repair from digital to memory circuits. Discusses future nanotechnology test trends and challenges facing the nanometer design era; promising nanotechnology test techniques, including Quantum-Dots, Cellular Automata, Carbon-Nanotubes, and Hybrid Semiconductor/Nanowire/Molecular Computing. Practical problems at the end of each chapter for students.
