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Author : 簡豪廷
Publisher :
ISBN 13 :
Total Pages : 97 pages
Book Rating : 4.:/5 (18 download)
Download or read book A Low Power 10-Bit SAR ADC with DT-MOS at Ultra-Low Supply Voltage written by 簡豪廷 and published by . This book was released on 2018 with total page 97 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Author : Taimur Rabuske
Publisher : Springer
ISBN 13 : 3319396242
Total Pages : 173 pages
Book Rating : 4.3/5 (193 download)
Download or read book Charge-Sharing SAR ADCs for Low-Voltage Low-Power Applications written by Taimur Rabuske and published by Springer. This book was released on 2016-08-02 with total page 173 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book introduces readers to the potential of charge-sharing (CS) successive approximation register (SAR) analog-to-digital converters (ADCs), while providing extensive analysis of the factors that limit the performance of the CS topology. The authors present guidelines and useful techniques for mitigating the limitations of the architecture, while focusing on the implementation under restricted power budgets and voltage supplies.
Author : Suresh Koyada
Publisher :
ISBN 13 :
Total Pages : 176 pages
Book Rating : 4.:/5 (962 download)
Download or read book Implementation of a 10-bit A-SAR ADC Circuit Based on Voltage to Time Conversion written by Suresh Koyada and published by . This book was released on 2016 with total page 176 pages. Available in PDF, EPUB and Kindle. Book excerpt: Comparators are widely used in analog to digital converters. However, the scaling of CMOS technologies makes the design of low power voltage comparators difficult. In order to overcome this problem time-based comparators are introduced which are suitable for nanometer CMOS technology and low supply voltages. This thesis presents the transistor level implementation of a 10-bit time-based accelerated SAR ADC with a supply voltage of 0.5 V. The design increases the conversion speed compared to conventional SAR ADC by updating the upper bound and lower bound of the search space more aggressively. Various design issues, including optimal switch design, glitch minimization at the charge scaling capacitor array output are discussed. This design achieves a SNDR of 58.78dB at a sampling rate of 90.9kS/s and ENOB (effective number of bits) of 9.47 bits with a power consumption of 280nW.
Author : Zhiheng Cao
Publisher : Springer Science & Business Media
ISBN 13 : 1402084501
Total Pages : 95 pages
Book Rating : 4.4/5 (2 download)
Download or read book Low-Power High-Speed ADCs for Nanometer CMOS Integration written by Zhiheng Cao and published by Springer Science & Business Media. This book was released on 2008-07-15 with total page 95 pages. Available in PDF, EPUB and Kindle. Book excerpt: Low-Power High-Speed ADCs for Nanometer CMOS Integration is about the design and implementation of ADC in nanometer CMOS processes that achieve lower power consumption for a given speed and resolution than previous designs, through architectural and circuit innovations that take advantage of unique features of nanometer CMOS processes. A phase lock loop (PLL) clock multiplier has also been designed using new circuit techniques and successfully tested. 1) A 1.2V, 52mW, 210MS/s 10-bit two-step ADC in 130nm CMOS occupying 0.38mm2. Using offset canceling comparators and capacitor networks implemented with small value interconnect capacitors to replace resistor ladder/multiplexer in conventional sub-ranging ADCs, it achieves 74dB SFDR for 10MHz and 71dB SFDR for 100MHz input. 2) A 32mW, 1.25GS/s 6-bit ADC with 2.5GHz internal clock in 130nm CMOS. A new type of architecture that combines flash and SAR enables the lowest power consumption, 6-bit >1GS/s ADC reported to date. This design can be a drop-in replacement for existing flash ADCs since it does require any post-processing or calibration step and has the same latency as flash. 3) A 0.4ps-rms-jitter (integrated from 3kHz to 300MHz offset for >2.5GHz) 1-3GHz tunable, phase-noise programmable clock-multiplier PLL for generating sampling clock to the SAR ADC. A new loop filter structure enables phase error preamplification to lower PLL in-band noise without increasing loop filter capacitor size.
Download or read book A 0.5-V 9.3-ENOB 68-nW 10-kS/s SAR ADC in 0.18-μm CMOS for Biomedical Applications written by and published by . This book was released on 2017 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: Abstract: This paper presents a 10-bit ultra-low power successive approximation register (SAR) analog-to-digital converter (ADC) intended for use in wearable biomedical circuits. In order to achieve the nanowatt range power consumption, an energy-efficiency modified VCM -based switching scheme is proposed. In addition, a fully dynamic comparator and a dynamic register are used to eliminate the static power consumption. To improve the signal linearity in such a low supply voltage, a double-boost bootstrapped switch is proposed. A prototype of the proposed SAR ADC was fabricated in 0.18 μm 1P6M CMOS technology within a bio-sensor front-end circuit, which occupies an active area of 370×390 μm 2 . The SAR ADC achieves 57.8 dB SNDR and consumes 68nW at 0.5 V supply voltage and 10 kHz sampling rate, resulting in a figure-of-merits (FOM) of 10.8fJ/conversion-step.
![Download A Low-voltage Low-power 10-bit Pipeline ADC in 90nm Digital CMOS Technology [microform] PDF Online Free](https://books.google.com/books/content/images/frontcover/fpNwtgAACAAJ?fife=w200-h370)
Author : Robert Wang
Publisher : Library and Archives Canada = Bibliothèque et Archives Canada
ISBN 13 : 9780612953710
Total Pages : 110 pages
Book Rating : 4.9/5 (537 download)
Download or read book A Low-voltage Low-power 10-bit Pipeline ADC in 90nm Digital CMOS Technology [microform] written by Robert Wang and published by Library and Archives Canada = Bibliothèque et Archives Canada. This book was released on 2004 with total page 110 pages. Available in PDF, EPUB and Kindle. Book excerpt: This design demonstrates that a single standard digital power supply solution for a 10-bit pipeline ADC is possible at low supply voltages in deep sub-micron CMOS technology. Measurement results show that this design is capable of sampling at 12 MS/s achieving a peak signal to noise and distortion ratio (SNDR) of 52.6dB using a 1.2V supply. It consumes only 3.3mW. The continuous trend in shrinking transistor size and reducing power supply voltage has prompted an increasing demand for low voltage analog circuit designs. A novel switched buffer switching technique in complimentary metal oxide semiconductor (CMOS) has been implemented for switched capacitor circuits in a low voltage low power 10-bit pipeline analog to digital converter (ADC) designed in 90 nanometer (nm) digital only CMOS technology with no analog enhancement.
Author : Zhili Pan
Publisher :
ISBN 13 :
Total Pages : 0 pages
Book Rating : 4.:/5 (137 download)
Download or read book A Low-power, Low-area 10-bit SAR ADC with Length-based Capacitive DAC written by Zhili Pan and published by . This book was released on 2022 with total page 0 pages. Available in PDF, EPUB and Kindle. Book excerpt: A 2.5 V single-ended 10-bit successive-approximation-register analog-to-digital converter (SAR ADC) based on the TSMC 65 nm CMOS process is designed with the goal of achieving low power consumption (33.63 pJ/sample) and small area (2874 μm2 ). It utilizes a novel length-based capacitive digital-to-analog converter (CDAC) layout to achieve low total capacitance for power efficiency, and a custom static asynchronous logic to free the dependence on a high-frequency external clock source. Two test chips have been designed and the problems found through testing the first chip are analyzed. Multiple improved versions of the ADC with minor variations are implemented on the second test chip for performance evaluation, and the test method is explained.
Author : Imran Ahmed
Publisher : Springer Science & Business Media
ISBN 13 : 9048186528
Total Pages : 225 pages
Book Rating : 4.0/5 (481 download)
Download or read book Pipelined ADC Design and Enhancement Techniques written by Imran Ahmed and published by Springer Science & Business Media. This book was released on 2010-03-10 with total page 225 pages. Available in PDF, EPUB and Kindle. Book excerpt: Pipelined ADCs have seen phenomenal improvements in performance over the last few years. As such, when designing a pipelined ADC a clear understanding of the design tradeoffs, and state of the art techniques is required to implement today's high performance low power ADCs.
Author : Mikko E. Waltari
Publisher : Springer Science & Business Media
ISBN 13 : 0306479796
Total Pages : 256 pages
Book Rating : 4.3/5 (64 download)
Download or read book Circuit Techniques for Low-Voltage and High-Speed A/D Converters written by Mikko E. Waltari and published by Springer Science & Business Media. This book was released on 2005-12-30 with total page 256 pages. Available in PDF, EPUB and Kindle. Book excerpt: This useful monograph presents a total of seven prototypes: two double-sampled S/H circuits, a time-interleaved ADC, an IF-sampling self-calibrated pipelined ADC, a current steering DAC with a deglitcher, and two pipelined ADCs employing the SO techniques.
Author : 楊孟法
Publisher :
ISBN 13 :
Total Pages : 144 pages
Book Rating : 4.:/5 (71 download)
Download or read book A 10-bit 27-MS/s Low Power SAR ADC written by 楊孟法 and published by . This book was released on 2010 with total page 144 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Author : Olga Kardonik
Publisher :
ISBN 13 :
Total Pages : 126 pages
Book Rating : 4.:/5 (865 download)
Download or read book A Study of SAR ADC and Implementation of 10-bit Asynchronous Design written by Olga Kardonik and published by . This book was released on 2013 with total page 126 pages. Available in PDF, EPUB and Kindle. Book excerpt: Successive Approximation Register (SAR) Analog-to-Digital Converters (ADCs) achieve low power consumption due to its simple architecture based on dominant digital content. SAR ADCs do not require an op-amp, so they are advantageous in CMOS technology scaling. The architecture is often the best choice for battery-powered or mobile applications which need medium resolution (8-12 bits), medium speed (10 - 100 MS/s) and require low-power consumption and small form factor. This work studies the architecture in depth, highlighting its main constraints and tradeoffs involving into SAR ADC design. The work researches asynchronous operation of SAR logic and investigates the latest trends for ADC's analog components - comparator and DAC. 10-bit asynchronous SAR ADC is implemented in CMOS 0.18 μm. Design's noise and power are presented as a breakdown among components.
Author : Hai Huang (Ph.D.)
Publisher :
ISBN 13 :
Total Pages : pages
Book Rating : 4.:/5 (13 download)
Download or read book High-speed and Low-power Pipelined SAR ADCs with Passive Residue Transfer and Dynamic Amplifier written by Hai Huang (Ph.D.) and published by . This book was released on 2017 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: High speed analog to digital converters (ADCs) are critical blocks in wideband wireline and wireless communication systems. This dissertation presents the designs of two high-speed pipelined successive-approximation-register (SAR) ADCs with the passive residue transfer technique and the process, voltage and temperature (PVT) stabilized dynamic amplifier. The passive residue transfer technique can effectively and efficiently replace the bandwidth-limiting residue amplifier in the medium-resolution pipelined SAR ADC. As a result, the time and power consumption associated with residue amplification are mostly removed and the ADC can obtain considerable speed improvement. Although dynamic amplifiers are employed in recent published pipelined SAR ADCs to achieve fast residue amplifications, the gain instability still limits the ADC's conversion accuracy when the supply voltage and ambient temperature varies. A PVT-stabilized dynamic amplifier based on the replica technique is reported to mitigate the gain variation over process, voltage and temperature changes. The first design is an 8 bit 1.2 GS/s pipelined SAR ADC with the passive residue transfer. It also utilizes the 2b-1b/cycle hybrid conversion scheme with an appropriate resolution partition to further enhance the conversion speed. The prototype ADC measured a signal-to-noise plus distortion ratio (SNDR) of 43.7 dB and a spurious-free dynamic range (SFDR) of 58.1 dB for a Nyquist input. The ADC consumes the total power dissipation of 5.0 mW and achieves a Walden FoM of 35 fJ/conversion-step at a sample rate of 1.2 GS/s. Although it is fabricated with a 65 nm process, the prototype ADC still achieves the same conversion speed as prior research works fabricated in a 32 nm process. The PVT-stabilized dynamic amplification technique is experimentally validated by the second ADC which is a 12 bit 330 MS/s pipelined-SAR ADC also in 65 nm CMOS. The maximum measured gain variations are 1.5% and 1.2% for the supply voltage varying from 1.25 V to 1.35 V and the temperature varying from −5 oC to 85 oC, respectively; the corresponding SNDR variations of the ADC are
Author : Paridhi Gulati
Publisher :
ISBN 13 :
Total Pages : 112 pages
Book Rating : 4.:/5 (14 download)
Download or read book A 10-bit, 10Msps Pipelined ADC with First Stage Conventional SAR ADC and Second Stage Multi-bit Per Cycle SAR ADC written by Paridhi Gulati and published by . This book was released on 2016 with total page 112 pages. Available in PDF, EPUB and Kindle. Book excerpt: A pipelined ADC is generally used for high speeds and high resolutions in applications where latency is not a major concern. This project involves the design of a 10 bit pipelined ADC with a conventional SAR ADC as stage one. The first stage also has an integrated comparator and amplifier. A dynamic automatic gain control scheme is used for the amplification of the first stage residue voltage. Techniques such as redundancy help in achieving higher speed while bidirectional single side switching helps in reducing power consumption. The second stage is a 3 bit per cycle SAR ADC that makes use of a scaled down version of the voltage supply. The ADC designed in this project makes use of 0.13um CMOS technology and is able to achieve a sampling rate of 10MS/s and ENOB of 9.95.
![Download Design of a Low Voltage, Micro Power Algarithmic [sic] Analog to Digital Converter PDF Online Free](https://books.google.com/books/content/images/frontcover/4iCrnQEACAAJ?fife=w200-h370)
Author : Christopher John Wichman
Publisher :
ISBN 13 :
Total Pages : 144 pages
Book Rating : 4.:/5 (841 download)
Download or read book Design of a Low Voltage, Micro Power Algarithmic [sic] Analog to Digital Converter written by Christopher John Wichman and published by . This book was released on 2005 with total page 144 pages. Available in PDF, EPUB and Kindle. Book excerpt: This thesis presents design techniques that enable the realization of micro-power algorithmic ADCs with potential applications in implantable biomedical devices and autonomous wireless sensor networks. Digital calibration and switched amplifiers are employed to reduce the analog power requirements. Additionally, the ADC is operated at a low voltage to minimize the digital power dissipation. Clock boosting, dc common mode level shifting, and an inversion coefficient based amplifier design methodology facilitate analog operation at low supply voltages. Simulation results indicate that a 10-bit, 50 kS/s converter realized in 0.5-[mu]m CMOS dissipates 41 [mu]W of power operating at a supply of 1.5 V. Measured results show the gain-by-two amplifier and low voltage comparators to be functional.
Author :
Publisher :
ISBN 13 :
Total Pages : 106 pages
Book Rating : 4.:/5 (935 download)
Download or read book A 10-bit 100-kS/s Low Power SAR ADC with LSB Boosted Technique written by and published by . This book was released on 2015 with total page 106 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Author : Samir Dutt
Publisher :
ISBN 13 :
Total Pages : 96 pages
Book Rating : 4.:/5 (74 download)
Download or read book A Novel 10-bit Hybrid ADC Using Flash and Delay Line Architectures written by Samir Dutt and published by . This book was released on 2011 with total page 96 pages. Available in PDF, EPUB and Kindle. Book excerpt: This thesis describes the architecture and implementation of a novel 10-bit hybrid Analog to Digital Converter using Flash and Delay Line concepts. Flash ADCs employ power hungry comparators which increase the overall power consumption of a high resolution ADC. High resolution flash also requires precision analog circuit design. Delay line ADCs are based on digital circuits and operate at low power. Both Flash based ADCs and delay line based ADCs can be used to get a fast analog to digital conversion, but with limited resolution. These two approaches are combined to achieve a 10-bit resolution (4 bits using Flash and 6 bits using delay line) without compromising on speed and maintaining low power operation. Low resolution of Flash also helps in reducing the analog circuit design complexity of the voltage comparators. The ADC was capable of running at 100M samples/s, with an ENOB of 8.82 bits, consuming 8.59mW at 1.8V.
Download or read book A 100 MS/s 9 Bit 0.43 MW SAR ADC with Custom Capacitor Array*Project Supported by the National High-Tech Research and Development Program of China (No. 2013AA014101). written by and published by . This book was released on 2016 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: Abstract: A low power 9 bit 100 MS/s successive approximation register analog-to-digital converter (SAR ADC) with custom capacitor array is presented. A brand-new 3-D MOM unit capacitor is used as the basic capacitor cell of this capacitor array. The unit capacitor has a capacitance of 1 fF. Besides, the advanced capacitor array structure and switch mode decrease the power consumption a lot. To verify the effectiveness of this low power design, the 9 bit 100 MS/s SAR ADC is implemented in TSMC IP9M 65 nm LP CMOS technology. The measurement results demonstrate that this design achieves an effective number of bits (ENOB) of 7.4 bit, a signal-to-noise plus distortion ratio (SNDR) of 46.40 dB and a spurious-free dynamic range (SFDR) of 62.31 dB at 100 MS/s with 1 MHz input. The SAR ADC core occupies an area of 0.030 mm 2 and consumes 0.43 mW under a supply voltage of 1.2 V. The figure of merit (FOM) of the SAR ADC achieves 23.75 fJ/conv.
