Testing for Delay Defects Utilizing Test Data Compression Techniques

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ISBN 13 :
Total Pages : 164 pages
Book Rating : 4.:/5 (244 download)

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Book Synopsis Testing for Delay Defects Utilizing Test Data Compression Techniques by : Richard Dean Putman

Download or read book Testing for Delay Defects Utilizing Test Data Compression Techniques written by Richard Dean Putman and published by . This book was released on 2008 with total page 164 pages. Available in PDF, EPUB and Kindle. Book excerpt: As technology shrinks new types of defects are being discovered and new fault models are being created for those defects. Transition delay and path delay fault models are two such models that have been created, but they still fall short in that they are unable to obtain a high test coverage of smaller delay defects; these defects can cause functional behavior to fail and also indicate potential reliability issues. The first part of this dissertation addresses these problems by presenting an enhanced timing-based delay fault testing technique that incorporates the use of standard delay ATPG, along with timing information gathered from standard static timing analysis. Utilizing delay fault patterns typically increases the test data volume by 3-5X when compared to stuck-at patterns. Combined with the increase in test data volume associated with the increase in gate count that typically accompanies the miniaturization of technology, this adds up to a very large increase in test data volume that directly affect test time and thus the manufacturing cost. The second part of this dissertation presents a technique for improving test compression and reducing test data volume by using multiple expansion ratios while determining the configuration of the scan chains for each of the expansion ratios using a dependency analysis procedure that accounts for structural dependencies as well as free variable dependencies to improve the probability of detecting faults. Finally, this dissertation addresses the problem of unknown values (X's) in the output response data corrupting the data and degrading the performance of the output response compactor and thus the overall amount of test compression. Four techniques are presented that focus on handling response data with large percentages of X's. The first uses X-canceling MISR architecture that is based on deterministically observing scan cells, and the second is a hybrid approach that combines a simple X-masking scheme with the X-canceling MISR for further gains in test compression. The third and fourth techniques revolve around reiterative LFSR X-masking, which take advantage of LFSR-encoded masks that can be reused for multiple scan slices in novel ways.

Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits

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Publisher : CRC Press
ISBN 13 : 1351833707
Total Pages : 266 pages
Book Rating : 4.3/5 (518 download)

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Book Synopsis Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits by : Sandeep K. Goel

Download or read book Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits written by Sandeep K. Goel and published by CRC Press. This book was released on 2017-12-19 with total page 266 pages. Available in PDF, EPUB and Kindle. Book excerpt: Advances in design methods and process technologies have resulted in a continuous increase in the complexity of integrated circuits (ICs). However, the increased complexity and nanometer-size features of modern ICs make them susceptible to manufacturing defects, as well as performance and quality issues. Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits covers common problems in areas such as process variations, power supply noise, crosstalk, resistive opens/bridges, and design-for-manufacturing (DfM)-related rule violations. The book also addresses testing for small-delay defects (SDDs), which can cause immediate timing failures on both critical and non-critical paths in the circuit. Overviews semiconductor industry test challenges and the need for SDD testing, including basic concepts and introductory material Describes algorithmic solutions incorporated in commercial tools from Mentor Graphics Reviews SDD testing based on "alternative methods" that explores new metrics, top-off ATPG, and circuit topology-based solutions Highlights the advantages and disadvantages of a diverse set of metrics, and identifies scope for improvement Written from the triple viewpoint of university researchers, EDA tool developers, and chip designers and tool users, this book is the first of its kind to address all aspects of SDD testing from such a diverse perspective. The book is designed as a one-stop reference for current industrial practices, research challenges in the domain of SDD testing, and recent developments in SDD solutions.

Test and Diagnosis for Small-Delay Defects

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Publisher : Springer Science & Business Media
ISBN 13 : 1441982973
Total Pages : 228 pages
Book Rating : 4.4/5 (419 download)

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Book Synopsis Test and Diagnosis for Small-Delay Defects by : Mohammad Tehranipoor

Download or read book Test and Diagnosis for Small-Delay Defects written by Mohammad Tehranipoor and published by Springer Science & Business Media. This book was released on 2011-09-08 with total page 228 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book will introduce new techniques for detecting and diagnosing small-delay defects in integrated circuits. Although this sort of timing defect is commonly found in integrated circuits manufactured with nanometer technology, this will be the first book to introduce effective and scalable methodologies for screening and diagnosing small-delay defects, including important parameters such as process variations, crosstalk, and power supply noise.

Dissertation Abstracts International

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Publisher :
ISBN 13 :
Total Pages : 810 pages
Book Rating : 4.F/5 ( download)

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Book Synopsis Dissertation Abstracts International by :

Download or read book Dissertation Abstracts International written by and published by . This book was released on 2009 with total page 810 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Hybrid Code-Based Test Data Compression and Decompression for VLSI Circuits

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Publisher :
ISBN 13 : 9783668737501
Total Pages : 218 pages
Book Rating : 4.7/5 (375 download)

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Book Synopsis Hybrid Code-Based Test Data Compression and Decompression for VLSI Circuits by : Kalamani Chinnappa Gounder

Download or read book Hybrid Code-Based Test Data Compression and Decompression for VLSI Circuits written by Kalamani Chinnappa Gounder and published by . This book was released on 2018-06-23 with total page 218 pages. Available in PDF, EPUB and Kindle. Book excerpt: Doctoral Thesis / Dissertation from the year 2018 in the subject Computer Science - Applied, grade: 6, Anna University, course: PhD, language: English, abstract: Test data compression is an effective method for reducing test data volume and memory requirement with relatively small cost. An effective test structure for embedded hard cores is easy to implement and it is also capable of producing high-quality tests as part of the design flow. The purpose of Test data compression intends to reduce Test data volume by using Test Stimulus Compression such as Code-based schemes, Linear-decompression-based schemes and Broadcast-scan-based schemes. The research work addresses the problem of the test data volume and memory requirements. The primary objective of this study is to introduce novel techniques that improve the compression ratio by reducing test data volume during at-speed test in scan designs. This in turn diminishes the tester memory requirement and hence chip area is reduced for Built-in-Self Test environment. The aim of this research is to introduce various compression algorithms by combining the existing data compression techniques. The algorithms are designed to reduce the volume of test patterns of input that is essential to guarantee an acceptable level of fault coverage which is a key parameter to evaluate the quality of testing.

System-on-Chip Test Architectures

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Publisher : Morgan Kaufmann
ISBN 13 : 0080556809
Total Pages : 893 pages
Book Rating : 4.0/5 (85 download)

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Book Synopsis System-on-Chip Test Architectures by : Laung-Terng Wang

Download or read book System-on-Chip Test Architectures written by Laung-Terng Wang and published by Morgan Kaufmann. This book was released on 2010-07-28 with total page 893 pages. Available in PDF, EPUB and Kindle. Book excerpt: Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today's overall product cost. This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and VLSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs. Emphasizes VLSI Test principles and Design for Testability architectures, with numerous illustrations/examples. Most up-to-date coverage available, including Fault Tolerance, Low-Power Testing, Defect and Error Tolerance, Network-on-Chip (NOC) Testing, Software-Based Self-Testing, FPGA Testing, MEMS Testing, and System-In-Package (SIP) Testing, which are not yet available in any testing book. Covers the entire spectrum of VLSI testing and DFT architectures, from digital and analog, to memory circuits, and fault diagnosis and self-repair from digital to memory circuits. Discusses future nanotechnology test trends and challenges facing the nanometer design era; promising nanotechnology test techniques, including Quantum-Dots, Cellular Automata, Carbon-Nanotubes, and Hybrid Semiconductor/Nanowire/Molecular Computing. Practical problems at the end of each chapter for students.

Power-Aware Testing and Test Strategies for Low Power Devices

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Publisher : Springer Science & Business Media
ISBN 13 : 1441909281
Total Pages : 376 pages
Book Rating : 4.4/5 (419 download)

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Book Synopsis Power-Aware Testing and Test Strategies for Low Power Devices by : Patrick Girard

Download or read book Power-Aware Testing and Test Strategies for Low Power Devices written by Patrick Girard and published by Springer Science & Business Media. This book was released on 2010-03-11 with total page 376 pages. Available in PDF, EPUB and Kindle. Book excerpt: Managing the power consumption of circuits and systems is now considered one of the most important challenges for the semiconductor industry. Elaborate power management strategies, such as dynamic voltage scaling, clock gating or power gating techniques, are used today to control the power dissipation during functional operation. The usage of these strategies has various implications on manufacturing test, and power-aware test is therefore increasingly becoming a major consideration during design-for-test and test preparation for low power devices. This book explores existing solutions for power-aware test and design-for-test of conventional circuits and systems, and surveys test strategies and EDA solutions for testing low power devices.

Nanometer Technology Designs

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Publisher : Springer Science & Business Media
ISBN 13 : 0387757287
Total Pages : 288 pages
Book Rating : 4.3/5 (877 download)

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Book Synopsis Nanometer Technology Designs by : Nisar Ahmed

Download or read book Nanometer Technology Designs written by Nisar Ahmed and published by Springer Science & Business Media. This book was released on 2010-02-26 with total page 288 pages. Available in PDF, EPUB and Kindle. Book excerpt: Traditional at-speed test methods cannot guarantee high quality test results as they face many new challenges. Supply noise effects on chip performance, high test pattern volume, small delay defect test pattern generation, high cost of test implementation and application, and utilizing low-cost testers are among these challenges. This book discusses these challenges in detail and proposes new techniques and methodologies to improve the overall quality of the transition fault test.

Electronic Design Automation for IC System Design, Verification, and Testing

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Publisher : CRC Press
ISBN 13 : 1482254638
Total Pages : 644 pages
Book Rating : 4.4/5 (822 download)

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Book Synopsis Electronic Design Automation for IC System Design, Verification, and Testing by : Luciano Lavagno

Download or read book Electronic Design Automation for IC System Design, Verification, and Testing written by Luciano Lavagno and published by CRC Press. This book was released on 2017-12-19 with total page 644 pages. Available in PDF, EPUB and Kindle. Book excerpt: The first of two volumes in the Electronic Design Automation for Integrated Circuits Handbook, Second Edition, Electronic Design Automation for IC System Design, Verification, and Testing thoroughly examines system-level design, microarchitectural design, logic verification, and testing. Chapters contributed by leading experts authoritatively discuss processor modeling and design tools, using performance metrics to select microprocessor cores for integrated circuit (IC) designs, design and verification languages, digital simulation, hardware acceleration and emulation, and much more. New to This Edition: Major updates appearing in the initial phases of the design flow, where the level of abstraction keeps rising to support more functionality with lower non-recurring engineering (NRE) costs Significant revisions reflected in the final phases of the design flow, where the complexity due to smaller and smaller geometries is compounded by the slow progress of shorter wavelength lithography New coverage of cutting-edge applications and approaches realized in the decade since publication of the previous edition—these are illustrated by new chapters on high-level synthesis, system-on-chip (SoC) block-based design, and back-annotating system-level models Offering improved depth and modernity, Electronic Design Automation for IC System Design, Verification, and Testing provides a valuable, state-of-the-art reference for electronic design automation (EDA) students, researchers, and professionals.

Thermal-Aware Testing of Digital VLSI Circuits and Systems

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Publisher : CRC Press
ISBN 13 : 1351227769
Total Pages : 86 pages
Book Rating : 4.3/5 (512 download)

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Book Synopsis Thermal-Aware Testing of Digital VLSI Circuits and Systems by : Santanu Chattopadhyay

Download or read book Thermal-Aware Testing of Digital VLSI Circuits and Systems written by Santanu Chattopadhyay and published by CRC Press. This book was released on 2018-04-24 with total page 86 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book aims to highlight the research activities in the domain of thermal-aware testing. Thermal-aware testing can be employed both at circuit level and at system level Describes range of algorithms for addressing thermal-aware test issue, presents comparison of temperature reduction with power-aware techniques and include results on benchmark circuits and systems for different techniques This book will be suitable for researchers working on power- and thermal-aware design and the testing of digital VLSI chips

Design and Test Technology for Dependable Systems-on-chip

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Publisher : IGI Global
ISBN 13 : 1609602145
Total Pages : 550 pages
Book Rating : 4.6/5 (96 download)

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Book Synopsis Design and Test Technology for Dependable Systems-on-chip by : Raimund Ubar

Download or read book Design and Test Technology for Dependable Systems-on-chip written by Raimund Ubar and published by IGI Global. This book was released on 2011-01-01 with total page 550 pages. Available in PDF, EPUB and Kindle. Book excerpt: "This book covers aspects of system design and efficient modelling, and also introduces various fault models and fault mechanisms associated with digital circuits integrated into System on Chip (SoC), Multi-Processor System-on Chip (MPSoC) or Network on Chip (NoC)"--

Asian Test Symposium

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Publisher :
ISBN 13 :
Total Pages : 526 pages
Book Rating : 4.3/5 (91 download)

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Book Synopsis Asian Test Symposium by :

Download or read book Asian Test Symposium written by and published by . This book was released on 2005 with total page 526 pages. Available in PDF, EPUB and Kindle. Book excerpt:

Program Management for System on Chip Platforms

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Publisher : First Books
ISBN 13 : 1592994830
Total Pages : 314 pages
Book Rating : 4.5/5 (929 download)

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Book Synopsis Program Management for System on Chip Platforms by : Whitson G. Waldo

Download or read book Program Management for System on Chip Platforms written by Whitson G. Waldo and published by First Books. This book was released on 2010-09 with total page 314 pages. Available in PDF, EPUB and Kindle. Book excerpt: A Fully Integrated Presentation of New Hardware and Software Product Introductions Using Program Management Methodologies for System on Chip Platforms If you're an executive, manager, or engineer in the semiconductor, software, or systems industries, this book provides conceptual views ranging from the design of integrated circuits or systems on a chip, through fabrication, to integration of chips onto boards, and through development of enablement and runtime software for system and platform deliveries. Special features included this book are: - Program management methodologies - General management fundamentals - An overview of leadership principles - Basic discrete device technology - Internal structure and operation of some common logic gates - Basic integrated circuit design concepts, building blocks, and flow - Chip packaging technologies - Details of the fabrication process for integrated circuits - Printed circuit board design, manufacture, and test - Software design, development, and test - Integrated circuit test, silicon validation, and device qualification - Program management applications bringing it all together The book explores interactions and dependencies of technologies that impact systems and platforms. This is a valuable resource to learn these technologies or to use as a reference.

Embedded Processor-Based Self-Test

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Publisher : Springer Science & Business Media
ISBN 13 : 9781402027857
Total Pages : 240 pages
Book Rating : 4.0/5 (278 download)

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Book Synopsis Embedded Processor-Based Self-Test by : Dimitris Gizopoulos

Download or read book Embedded Processor-Based Self-Test written by Dimitris Gizopoulos and published by Springer Science & Business Media. This book was released on 2004-12-20 with total page 240 pages. Available in PDF, EPUB and Kindle. Book excerpt: Embedded Processor-Based Self-Test is a guide to self-testing strategies for embedded processors. Embedded processors are regularly used today in most System-on-Chips (SoCs). Testing of microprocessors and embedded processors has always been a challenge because most traditional testing techniques fail when applied to them. This is due to the complex sequential structure of processor architectures, which consists of high performance datapath units and sophisticated control logic for performance optimization. Structured Design-for-Testability (DfT) and hardware-based self-testing techniques, which usually have a non-trivial impact on a circuit’s performance, size and power, can not be applied without serious consideration and careful incorporation into the processor design. Embedded Processor-Based Self-Test shows how the powerful embedded functionality that processors offer can be utilized as a self-testing resource. Through a discussion of different strategies the book emphasizes on the emerging area of Software-Based Self-Testing (SBST). SBST is based on the idea of execution of embedded software programs to perform self-testing of the processor itself and its surrounding blocks in the SoC. SBST is a low-cost strategy in terms of overhead (area, speed, power), development effort and test application cost, as it is applied using low-cost, low-speed test equipment. Embedded Processor-Based Self-Test can be used by designers, DfT engineers, test practitioners, researchers and students working on digital testing, and in particular processor and SoC test. This book sets the framework for comparisons among different SBST methodologies by discussing key requirements. It presents successful applications of SBST to a number of embedded processors of different complexities and instruction set architectures.

Scalable Test Generation for Path Delay Faults

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Publisher :
ISBN 13 :
Total Pages : 75 pages
Book Rating : 4.:/5 (437 download)

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Book Synopsis Scalable Test Generation for Path Delay Faults by : Edward Flanigan

Download or read book Scalable Test Generation for Path Delay Faults written by Edward Flanigan and published by . This book was released on 2009 with total page 75 pages. Available in PDF, EPUB and Kindle. Book excerpt: Modern day IC design has drawn a lot of attention towards the path delay fault model (PDF), which targets delay defects that affect the timing characteristics of a circuit. Due to the exponential number of paths in modern circuits a subset of critical paths are chosen for testing purposes. Path intensive circuits contain a large number of critical paths whose delays affect the performance of the circuit. This dissertation presents three techniques to improve test generation for path delay faults. The first technique presented in this dissertation avoids testing unnecessary paths by using arithmetic operations. The second technique shows how to compact many faults into a single test application, thus saving valuable test application time. The third technique demonstrates how to generate tests under modern day scan architectures. Experimental results demonstrate the effectiveness of the proposed techniques.

Index to IEEE Publications

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Publisher :
ISBN 13 :
Total Pages : 1234 pages
Book Rating : 4.3/5 (91 download)

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Book Synopsis Index to IEEE Publications by : Institute of Electrical and Electronics Engineers

Download or read book Index to IEEE Publications written by Institute of Electrical and Electronics Engineers and published by . This book was released on 1998 with total page 1234 pages. Available in PDF, EPUB and Kindle. Book excerpt: Issues for 1973- cover the entire IEEE technical literature.

Trace-Based Post-Silicon Validation for VLSI Circuits

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Publisher : Springer Science & Business Media
ISBN 13 : 3319005332
Total Pages : 118 pages
Book Rating : 4.3/5 (19 download)

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Book Synopsis Trace-Based Post-Silicon Validation for VLSI Circuits by : Xiao Liu

Download or read book Trace-Based Post-Silicon Validation for VLSI Circuits written by Xiao Liu and published by Springer Science & Business Media. This book was released on 2013-06-12 with total page 118 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book first provides a comprehensive coverage of state-of-the-art validation solutions based on real-time signal tracing to guarantee the correctness of VLSI circuits. The authors discuss several key challenges in post-silicon validation and provide automated solutions that are systematic and cost-effective. A series of automatic tracing solutions and innovative design for debug (DfD) techniques are described, including techniques for trace signal selection for enhancing visibility of functional errors, a multiplexed signal tracing strategy for improving functional error detection, a tracing solution for debugging electrical errors, an interconnection fabric for increasing data bandwidth and supporting multi-core debug, an interconnection fabric design and optimization technique to increase transfer flexibility and a DfD design and associated tracing solution for improving debug efficiency and expanding tracing window. The solutions presented in this book improve the validation quality of VLSI circuits, and ultimately enable the design and fabrication of reliable electronic devices.