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Successive Approximation Register Analog To Digital Converter For Low Power Cmos Image Sensing And Compression
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Book Synopsis Successive-approximation-register Analog-to-digital-converter for Low-power CMOS Image Sensing and Compression by : Denis Guangyin Chen
Download or read book Successive-approximation-register Analog-to-digital-converter for Low-power CMOS Image Sensing and Compression written by Denis Guangyin Chen and published by . This book was released on 2013 with total page 134 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis Low-power Techniques for Successive Approximation Register (SAR) Analog-to-digital Converters by : Ramgopal Sekar
Download or read book Low-power Techniques for Successive Approximation Register (SAR) Analog-to-digital Converters written by Ramgopal Sekar and published by . This book was released on 2010 with total page 160 pages. Available in PDF, EPUB and Kindle. Book excerpt: In this work, the author investigated circuit techniques to reduce the power consumption of Successive Approximation Register Analog-to-Digital Converter (SAR-ADC). The author developed four low-power SAR-ADC design techniques, which are: (1) Low-power SAR-ADC design with split voltage reference, (2) Charge recycling techniques for low-power SAR-ADC design, (3) Low-power SAR-ADC design using two-capacitor arrays, (4) Power reduction techniques by dynamically minimizing SAR-ADC conversion cycles. Matlab simulations are performed to investigate the power saving by the proposed techniques. Simulation results show that significant power reduction can be achieved by using the developed techniques. In addition, design issues such as area overhead, design complexity associated with the proposed low-power techniques are also discussed in the thesis.
Book Synopsis Low-power Successive Approximation Analog to Digital Converter with Digital Calibration by : Wei Li
Download or read book Low-power Successive Approximation Analog to Digital Converter with Digital Calibration written by Wei Li and published by . This book was released on 2014 with total page 73 pages. Available in PDF, EPUB and Kindle. Book excerpt: IC designers are continuously facing the challenges from reduced CMOS feature sizes and supply voltages. ADCs that deliver satisfactory resolutions/speeds while utilizing the state-of-the-art technologies to save power are in high demand. The analog circuits are more and more assisted by various digital calibration techniques to get boosted performances. This dissertation is focused on a low-power 12-bit 12.5-MS/s successive approximation (SAR) ADC with a couple of calibration schemes. The performances of the proposed SAR ADC are enhanced in two directions. To reduce the power dissipation, a power saving strategy has been proposed. Also, several foreground calibration methods for SAR ADCs have been proposed to reduce power dissipation and enhance conversion accuracy. The design was fabricated in 40nm CMOS technology. Measurement results after calibration showed a SFDR of 82.2 dB, and a THD improvement of 22.5 dB. Finally, two new schemes to realize teraohm on-chip resistance are presented. One of the schemes utilizes a switched-capacitor array, and the other utilizes a switch-capacitor ladder. Using these schemes, large resistances can be fabricated with standard CMOS process in an affordable chip area.
Book Synopsis A 16 Bit 500KSps Low Power Successive Approximation Analog to Digital Converter by : Kun Yang
Download or read book A 16 Bit 500KSps Low Power Successive Approximation Analog to Digital Converter written by Kun Yang and published by . This book was released on 2009 with total page 61 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis Time-interleaved Analog-to-Digital Converters by : Simon Louwsma
Download or read book Time-interleaved Analog-to-Digital Converters written by Simon Louwsma and published by Springer Science & Business Media. This book was released on 2010-09-08 with total page 148 pages. Available in PDF, EPUB and Kindle. Book excerpt: Time-interleaved Analog-to-Digital Converters describes the research performed on low-power time-interleaved ADCs. A detailed theoretical analysis is made of the time-interleaved Track & Hold, since it must be capable of handling signals in the GHz range with little distortion, and minimal power consumption. Timing calibration is not attractive, therefore design techniques are presented which do not require timing calibration. The design of power efficient sub-ADCs is addressed with a theoretical analysis of a successive approximation converter and a pipeline converter. It turns out that the first can consume about 10 times less power than the latter, and this conclusion is supported by literature. Time-interleaved Analog-to-Digital Converters describes the design of a high performance time-interleaved ADC, with much attention for practical design aspects, aiming at both industry and research. Measurements show best-inclass performance with a sample-rate of 1.8 GS/s, 7.9 ENOBs and a power efficiency of 1 pJ/conversion-step.
Book Synopsis Power Optimization of Algorithmic Analog-to-digital Converters by : Steven Daniel Tucker
Download or read book Power Optimization of Algorithmic Analog-to-digital Converters written by Steven Daniel Tucker and published by . This book was released on 2005 with total page 346 pages. Available in PDF, EPUB and Kindle. Book excerpt: This dissertation presents techniques for power optimization in algorithmic analog-to-digital converters (ADCs) enabling realization of ultra low power data converters. Implantable biomedical devices and autonomous wireless sensor networks are among the most rapidly growing applications that require low speed, medium resolution ADCs. Traditionally, successive approximation register ADC architectures have been used for low power data conversion. However, the successive approximation architecture suffers from limited resolution and design flexibility. This dissertation shows algorithmic ADCs are a better architectural choice for the above mentioned applications due to its compact layout and its inherent re-configurability. This dissertation shows the transfer of design complexity from the analog to the digital domain in algorithmic ADCs enables power-optimized designs. Use of digital calibration reduces the amplifier design specifications, thereby saving power, at a minimal cost of increase in digital power dissipation. The amplifier slew rate is controlled digitally, further reducing the amplifier power dissipation. Additionally, a CMOS inversion coefficient design methodology is shown to optimally realize the reduced amplifier specifications for a given power budget. The proposed techniques are experimentally verified using a 10-bit, 500 kS/s algorithmic ADCs fabricated in a 0.5-[mu]m bulk CMOS process. Measurement results indicate that the proposed design techniques show a power savings of more than 70% compared to standard algorithmic ADC design.
Book Synopsis Pipeline Analog-to-digital Converter Design in Scaled CMOS Technology by : Chen-Kai Hsu
Download or read book Pipeline Analog-to-digital Converter Design in Scaled CMOS Technology written by Chen-Kai Hsu and published by . This book was released on 2020 with total page 0 pages. Available in PDF, EPUB and Kindle. Book excerpt: Pipeline analog-to-digital converters (ADCs) are typically chosen for medium-to-high-resolution and high-bandwidth applications. Nevertheless, each generation of technology scaling, strongly driven by the demand for even more powerful digital computation capabilities, continuously entails a great challenge on the precision of the interstage gain in pipeline ADCs. The inaccurate interstage gain leads to the quantization leakage error in pipeline ADCs, which degrades the signal-to-noise-and-distortion ratio (SNDR) of pipeline ADCs. This dissertation demonstrates three techniques to address the inaccurate interstage gain in pipeline ADCs. To start with, an interstage gain error shaping (GES) technique is proposed. It can substantially suppress the in-band quantization leakage error in pipeline ADCs. It works for both closed-loop and open-loop amplification. It does not require extra clock phases, long convergence time, or an interruption of the digitization, incur large power or area overhead, or pose a constraint on the input signal. A two-stage pipeline successive-approximation-register (SAR) ADC equipped with the proposed second-order GES technique in 40-nm low-power (LP) CMOS technology achieves a 75.8-dB SNDR over 12.5-MHz bandwidth while operating at 100 MS/s and consuming 1.54 mW. It achieves a 174.9-dB Schreier figure of merit (FoM). The GES-related hardware only occupies less than 2% of the total active area. Next, an enhanced interstage GES technique that adopts a digital error feedback (DEF) method to address the truncation error in the prior implementation is proposed, which can extend the interstage gain error tolerance by five times. The proposed DEF technique does not introduce additional errors as it operates purely in the digital domain. In addition, a first-order passive quantization noise shaping (NS) technique that reduces the input-pair ratio of the two-input-pair comparator by 2.7 times is proposed. The proposed passive NS technique can alleviate the noise penalty caused by using a multiple-input-pair comparator. A two-stage pipeline SAR ADC equipped with the proposed techniques in 40-nm LP CMOS technology achieves a 77.1-dB SNDR over 6.25-MHz bandwidth while operating at 100 MS/s and consuming 1.38 mW. It achieves a 173.7-dB Schreier FoM. Finally, the use of foreground interstage gain calibration is demonstrated to address the inaccurate interstage gain in pipeline ADCs. It is implemented in a 13-bit 40-MS/s two-stage pipeline SAR ADC. The prototype ADC is designed for the phase-II readout electronics of the ATLAS liquid argon (LAr) calorimeter. To ensure its robustness under the harsh radioactive environment, several radiation-hardened techniques are implemented. To increase its yield, foreground digital-to-analog converter (DAC) mismatch calibration is also implemented. It is implemented in 65-nm LP CMOS technology. With the foreground calibration, it achieves an effective number of bits (ENOB) better than 11.2 bits over the bandwidth of interest while consuming 17.6 mW. Besides, on-chip high-speed reference buffers are deployed to avoid the need for large decoupling capacitors and provide stable reference voltages by tracking bandgap voltage references.
Book Synopsis Digitally Assisted Techniques for Nyquist Rate Analog-to-Digital Converters by : Rabeeh Majidi
Download or read book Digitally Assisted Techniques for Nyquist Rate Analog-to-Digital Converters written by Rabeeh Majidi and published by . This book was released on 2015 with total page 204 pages. Available in PDF, EPUB and Kindle. Book excerpt: Abstract: With the advance of technology and rapid growth of digital systems, low power high speed analog-to- digital converters with great accuracy are in demand. To achieve high effective number of bits Analog-to-Digital Converter (ADC) calibration as a time consuming process is a potential bottleneck for designs. This dissertation presentsa fully digital background calibration algorithm for a 7- bit redundant flash ADC using split structure and look-up table based correction. Redundant comparators are used in the flash ADC design of this work in order to tolerate large offset voltages while minimizing signal input capacitance. The split ADC structure helps by eliminating the unknown input signal from the calibration path. The flash ADC has been designed in 180nm IBM CMOS technology and fabricated through MOSIS. This work was supported by Analog Devices, Wilmington, MA. While much research on ADC design has concentrated on increasing resolution and sample rate, there are many applications (e.g. biomedical devices and sensor networks) that do not require high performance but do require low power energy efficient ADCs. This dissertation also explores on design of a low quiescent current 100k Sps Successive Approximation (SAR) ADC that has been used as an error detection ADC for an automotive application in 350nm CD (CMOS-DMOS) technology. This work was supported by ON Semiconductor Corp, East Greenwich, RI.
Book Synopsis Welcome to the World of Single-Slope Column-Level Analog-to-Digital Converters for CMOS Image Sensors by : Albert Theuwissen
Download or read book Welcome to the World of Single-Slope Column-Level Analog-to-Digital Converters for CMOS Image Sensors written by Albert Theuwissen and published by . This book was released on 2021-06-08 with total page 84 pages. Available in PDF, EPUB and Kindle. Book excerpt: CCMOS image sensors (CIS) have come a long way over the past decennia. The combination of an image sensor with on-chip column-level ADCs demonstrates exceptional performance as far as speed and power are concerned. This monograph gives an overview and background of the various developments of the SS-ADCs.
Book Synopsis An Implementation of 1.5 Bits/Stage Low Power Successive Approximation Register Analog to Digital Converter by Using on Chip Calibration by :
Download or read book An Implementation of 1.5 Bits/Stage Low Power Successive Approximation Register Analog to Digital Converter by Using on Chip Calibration written by and published by . This book was released on 2015 with total page 89 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis Comparator Power Reduction for Low Power Successive Approximation Analog to Digital Converters by : Muhammad Ahmadi
Download or read book Comparator Power Reduction for Low Power Successive Approximation Analog to Digital Converters written by Muhammad Ahmadi and published by . This book was released on 2015 with total page 144 pages. Available in PDF, EPUB and Kindle. Book excerpt: Many applications like sensor nodes, wireless communications and consumer products require analog-to-digital converters (ADCs) to digitize the analog information. Charge redistribution successive approximation register (SAR) ADC has been a popular candidate in these applications due to its simplicity, low power consumption, medium speed and resolution. The three primary components of a SAR ADC are the digital-to-analog converter (DAC), digital SAR logic, and comparator. The power consumption of the DAC can be greatly minimized by employing a small unit capacitor and digital circuits benefit from technology scaling. Consequently, the comparator has become a major source of power consumption in recent power efficient SAR ADCs. Two comparator power reduction techniques are proposed which are based on the observation that the comparator noise variance need not be the same for each bit cycle of the SAR ADC. So, the performance of the SAR ADC is analyzed rigorously assuming that the comparator thermal noise differs for each bit cycle. The mathematical model suggests that using the same comparator noise variance for each bit cycle is suboptimal and results in more power consumption than necessary. As a first technique, a noise programmable comparator based on majority vote technique is proposed to adjust the comparator noise performance at each bit step by changing the number of votes taken at each bit step. As a proof of concept, a 10b SAR ADC that operates at 0.5 V supply voltage and supports a flexible differential input dynamic range from 0.4 V to 1 V has been fabricated in 65nm CMOS process. Second, the optimal comparators that need to be used to achieve a desired overall performance at minimum power levels are theoretically analyzed. Simulation results show that up to 50% and 60% reduction in comparator power consumption for 10b and 12b SAR ADCs, respectively, can be achieved. To reduce the implementation complexity, the comparator noise allocation problem is also solved when fewer than N comparators are employed in an N-bit SAR ADC. Simulation results suggest that two comparators are sufficient to achieve near ideal performance.
Book Synopsis Low Power Successive-approximation Register ADC. by : 胡耀升
Download or read book Low Power Successive-approximation Register ADC. written by 胡耀升 and published by . This book was released on 2014 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis A Low-power 10-bit 50 MS/s CMOS Successive Approximation Register ADC. by : Wei Guo
Download or read book A Low-power 10-bit 50 MS/s CMOS Successive Approximation Register ADC. written by Wei Guo and published by . This book was released on 2012 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis Circuit Design for Realization of a 16 Bit 1MS/s Successive Approximation Register Analog-to-Digital Converter by : Cody R. Brenneman
Download or read book Circuit Design for Realization of a 16 Bit 1MS/s Successive Approximation Register Analog-to-Digital Converter written by Cody R. Brenneman and published by . This book was released on 2010 with total page 242 pages. Available in PDF, EPUB and Kindle. Book excerpt: Abstract: As the use of digital systems continues to grow, there is an increasing need to convert analog information into the digital domain. Successive Approximation Register (SAR) analog-to-digital converters are used extensively in this regard due to their high resolution, small die area, and moderate conversion speeds. However, capacitor mismatch within the SAR converter is a limiting factor in its accuracy and resolution. Without some form of calibration, a SAR converter can only reasonably achieve an accuracy of 10 bits. The Split-ADC technique is a digital, deterministic, background self-calibration algorithm that can be applied to the SAR converter. This thesis describes the circuit design and physical implementation of a novel 16-bit 1MS/s SAR analog-to-digital converter for use with the Split-ADC calibration algorithm. The system was designed using the Jazz 0.18um CMOS process, successfully operates at 1MS/s, and consumes a die area of 1.2mm2. The calibration algorithm was applied, showing an improvement in the overall accuracy of the converter.
Download or read book ISLPED'01 written by and published by . This book was released on 2001 with total page 416 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis Accelerated Successive Approximation Technique for Analog to Digital Converter Design by : Ram Harshvardhan Radhakrishnan
Download or read book Accelerated Successive Approximation Technique for Analog to Digital Converter Design written by Ram Harshvardhan Radhakrishnan and published by . This book was released on 2015 with total page 82 pages. Available in PDF, EPUB and Kindle. Book excerpt: This thesis work presents a novel technique to reduce the number of conversion cycles for Successive Approximation register (SAR) Analog to Digital Converters (ADC), thereby potentially improving the conversion speed as well as reducing its power consumption. Conventional SAR ADCs employ the binary search algorithm and they update only one bound, either the upper or lower bound, of the search space during one conversion cycle. The proposed method, referred to as the Accelerated-SAR or A-SAR, is capable of updating both the lower and upper bounds in a single conversion cycle. Even in cases that it can update only one bound, it does more aggressively. The proposed technique is implemented in a 10-bit SAR ADC circuit with 0.5V power supply and rail-to-rail input range. To cope with the ultra-low voltage design challenge, Time-to-Digital conversion techniques are used in the implementation. Important design issues are also discussed for the charge scaling array and Voltage Controlled Delay Lines (VCDL), which are important building blocks in the ADC implementation.
Book Synopsis Design Techniques for Low Power High Speed Successive Approximation Analog-to-digital Converters by : Jiaming Lin
Download or read book Design Techniques for Low Power High Speed Successive Approximation Analog-to-digital Converters written by Jiaming Lin and published by . This book was released on 2013 with total page 75 pages. Available in PDF, EPUB and Kindle. Book excerpt: This dissertation presents two high-speed pipeline successive approximation analog-to-digital converters (SAR ADCs). Capacitive DACs and resistive DACs are utilized in these two pipeline SAR ADCs, respectively. The pipeline SAR ADC with capacitive DACs can save 50% switching power compared with other time-interleaved SAR ADCs since the total capacitance of the DACs in this ADC is more than 50% less than the conventional time-interleave ones. Several switching techniques are implemented to alleviate the impact from the parasitic capacitance and improve the performance. The pipeline SAR ADC with resistive DACs overcomes the influence from the parasitic capacitance with negligible static power consumption on the resistive DACs. Also, the complicated switching techniques can be avoided to simplify the timing logic. To verify the above two architectures, two chips were designed and fabricated in 40nm CMOS process. Finally, a new architecture of multi-step capacitive-splitting SAR ADC is proposed for low power applications. By using two identical capacitor-splitting capacitor arrays, the switching power and capacitor area can be reduced significantly.
