Author : Mukund Sivaraman
Publisher :
ISBN 13 :
Total Pages : 107 pages
Book Rating : 4.:/5 (379 download)
Book Synopsis Signal Stabilization Analysis for Timing Verification and Delay Fault Testing by : Mukund Sivaraman
Download or read book Signal Stabilization Analysis for Timing Verification and Delay Fault Testing written by Mukund Sivaraman and published by . This book was released on 1997 with total page 107 pages. Available in PDF, EPUB and Kindle. Book excerpt: Abstract: "Present-day digital systems are characterized by large complexity, operation under tight timing constraints, numerous false paths, and large variations in component delays. In such a scenario, it is very important to ensure correct temporal behavior of these circuits, both before and after fabrication. For combinational circuits, it has been shown that it is necessary and sufficient to guarantee that the primitive path delay faults (primitive PDFs) are fault-free to ensure that the circuit operates correctly for some timing constraint T and all larger timing constraints, where primitive PDFs correspond to minimal sets of paths that are singly/jointly non-robustly testable. We show that primitive PDFs determine the stabilization time of the circuit outputs, based on which we develop a feasible method to identify the primitive PDFs in a general multilevel logic circuit. We also develop an approach to determine the maximum circuit delay using this primitive PDF identification mechanism, and prove that this delay is exactly equal to the maximum circuit delay found under the floating mode of operation assumption. Our timing analysis approach provides several advantages over previously reported floating mode timing analyzers: increased accuracy in the presence of component delay correlations and signal correlations arising from fabrication process, signal propagation, and signal interaction effects; increased efficiency in situations where critical paths need to be re- identified due to component delay speedup (e.g., post-layout delay optimization). We also present a framework for the diagnosis of circuit failures caused by distributed path delay faults. This involves determining the paths/sub-paths and fabrication process parameters that caused the chip failure. A metric to quantify the diagnosability of a path delay fault for a test is also proposed. Finally, we propose a very realistic metric for delay fault coverage which accounts for delay fault size distributions and is applicable to any delay fault model. We apply this metric to estimate the true delay fault coverage of robust test sets."