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Self Calibration And Digital Trimming Of Successive Approximation Analog To Digital Converters
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Book Synopsis Self-calibration and Digital-trimming of Successive Approximation Analog-to-digital Converters by : Shankar Thirunakkarasu
Download or read book Self-calibration and Digital-trimming of Successive Approximation Analog-to-digital Converters written by Shankar Thirunakkarasu and published by . This book was released on 2014 with total page 83 pages. Available in PDF, EPUB and Kindle. Book excerpt: Several state of the art, monitoring and control systems, such as DC motorcontrollers, power line monitoring and protection systems, instrumentation systems and battery monitors require direct digitization of a high voltage input signals. Analog-to-Digital Converters (ADCs) that can digitize high voltage signals require high linearity and low voltage coefficient capacitors. A built in self-calibration and digital-trim algorithm correcting static mismatches in Capacitive Digital-to-Analog Converter (CDAC) used in Successive Approximation Register Analog to Digital Converters (SARADCs) is proposed. The algorithm uses a dynamic error correction (DEC) capacitor to cancel the static errors occurring in each capacitor of the array as the first step upon power-up and eliminates the need for an extra calibration DAC. Self-trimming is performed digitally during normal ADC operation. The algorithm is implemented on a 14-bit high-voltage input range SAR ADC with integrated dynamic error correction capacitors. The IC is fabricated in 0.6-um high voltage compliant CMOS process, accepting up to 24Vpp differential input signal. The proposed approach achieves 73.32 dB Signal to Noise and Distortion Ratio (SNDR) which is an improvement of 12.03 dB after self-calibration at 400 kS/s sampling rate, consuming 90-mW from a +/-15V supply. The calibration circuitry occupies 28% of the capacitor DAC, and consumes less than 15mW during operation. Measurement results shows that this algorithm reduces INL from as high as 7 LSBs down to 1 LSB and it works even in the presence of larger mismatches exceeding 260 LSBs. Similarly, it reduces DNL errors from 10 LSBs down to 1 LSB. The ADC occupies an active area of 9.76 mm2.
Book Synopsis Self-calibration Techniques for Successive Approximation Analog-to-digital Converters by : Hae-Seung Lee
Download or read book Self-calibration Techniques for Successive Approximation Analog-to-digital Converters written by Hae-Seung Lee and published by . This book was released on 1984 with total page 356 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis Applying the "split-ADC" Architecture to a 16 Bit, 1 MS/s Differential Successive Approximation Analog-to-digital Converter by :
Download or read book Applying the "split-ADC" Architecture to a 16 Bit, 1 MS/s Differential Successive Approximation Analog-to-digital Converter written by and published by . This book was released on 2008 with total page 350 pages. Available in PDF, EPUB and Kindle. Book excerpt: Abstract: Successive Approximation (SAR) analog-to-digital converters are used extensively in biomedical applications such as CAT scan due to the high resolution they offer. Capacitor mismatch in the SAR converter is a limiting factor for its accuracy and resolution. Without some form of calibration, a SAR converter can only achieve 10 bit accuracy. In industry, the CAL-DAC approach is a popular approach for calibrating the SAR ADC, but this approach requires significant test time. This thesis applies the "Split-ADC" architecture with a deterministic, digital, and background self-calibration algorithm to the SAR converter to minimize test time. In this approach, a single ADC is split into two independent halves. The two split ADCs convert the same input sample and produce two output codes. The ADC output is the average of these two output codes. The difference between these two codes is used as a calibration signal to estimate the errors of the calibration parameters in a modified Jacobi method. The estimates are used to update calibration parameters are updated in a negative feedback LMS procedure. The ADC is fully calibrated when the difference signal goes to zero on average. This thesis focuses on the specific implementation of the "Split-ADC" self-calibrating algorithm on a 16 bit, 1 MS/s differential SAR ADC. The ADC can be calibrated with 105 conversions. This represents an improvement of 3 orders of magnitude over existing statistically-based calibration algorithms. Simulation results show that the linearity of the calibrated ADC improves to within "1 LSB.
Book Synopsis All Digital Calibration for High-resolution Successive-approximation Register Analog-to-digital Converter by : 廖亦勛
Download or read book All Digital Calibration for High-resolution Successive-approximation Register Analog-to-digital Converter written by 廖亦勛 and published by . This book was released on 2022 with total page 0 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis A Calibration Service for Analog-to-digital and Digital-to-analog Converters by : T. Michael Souders
Download or read book A Calibration Service for Analog-to-digital and Digital-to-analog Converters written by T. Michael Souders and published by . This book was released on 1981 with total page 84 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis Low-power Successive Approximation Analog to Digital Converter with Digital Calibration by : Wei Li
Download or read book Low-power Successive Approximation Analog to Digital Converter with Digital Calibration written by Wei Li and published by . This book was released on 2014 with total page 73 pages. Available in PDF, EPUB and Kindle. Book excerpt: IC designers are continuously facing the challenges from reduced CMOS feature sizes and supply voltages. ADCs that deliver satisfactory resolutions/speeds while utilizing the state-of-the-art technologies to save power are in high demand. The analog circuits are more and more assisted by various digital calibration techniques to get boosted performances. This dissertation is focused on a low-power 12-bit 12.5-MS/s successive approximation (SAR) ADC with a couple of calibration schemes. The performances of the proposed SAR ADC are enhanced in two directions. To reduce the power dissipation, a power saving strategy has been proposed. Also, several foreground calibration methods for SAR ADCs have been proposed to reduce power dissipation and enhance conversion accuracy. The design was fabricated in 40nm CMOS technology. Measurement results after calibration showed a SFDR of 82.2 dB, and a THD improvement of 22.5 dB. Finally, two new schemes to realize teraohm on-chip resistance are presented. One of the schemes utilizes a switched-capacitor array, and the other utilizes a switch-capacitor ladder. Using these schemes, large resistances can be fabricated with standard CMOS process in an affordable chip area.
Book Synopsis Advanced Analog-to-Digital and Digital-to-Analog Convertors by : Hae-Seung (Harry) Lee
Download or read book Advanced Analog-to-Digital and Digital-to-Analog Convertors written by Hae-Seung (Harry) Lee and published by Springer. This book was released on 2010-12-15 with total page 0 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book offers innovative techniques from a research group that has shaped the evolution of analog-to-digital converter design for two decades. It reviews creative approaches across a number of technologies. Coverage includes popular architectures such as pipeline, delta-sigma, successive-approximation, flash and algorithmic converters. The book explores architectural techniques for reducing power consumption and improving linearity and signal-to-noise ratio. These include self-calibration, commutative feedback and mismatch-shaping techniques.
Book Synopsis A Full Range Digital Calibration in 12-bit Successive Approximation Register Analog-to-Digital Converter by : 林葦婷
Download or read book A Full Range Digital Calibration in 12-bit Successive Approximation Register Analog-to-Digital Converter written by 林葦婷 and published by . This book was released on 2013 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis All Digital, Background Calibration for Time-Interleaved and Successive Approximation Register Analog-to-Digital Converters by : Christopher Leonidas David
Download or read book All Digital, Background Calibration for Time-Interleaved and Successive Approximation Register Analog-to-Digital Converters written by Christopher Leonidas David and published by . This book was released on 2010 with total page 370 pages. Available in PDF, EPUB and Kindle. Book excerpt: Abstract: The growth of digital systems underscores the need to convert analog information to the digital domain at high speeds and with great accuracy. Analog-to-Digital Converter (ADC) calibration is often a limiting factor, requiring longer calibration times to achieve higher accuracy. The goal of this dissertation is to perform a fully digital background calibration using an arbitrary input signal for A/D converters. The work presented here adapts the cyclic "Split-ADC" calibration method to the time interleaved (TI) and successive approximation register (SAR) architectures. The TI architecture has three types of linear mismatch errors: offset, gain and aperture time delay. By correcting all three mismatch errors in the digital domain, each converter is capable of operating at the fastest speed allowed by the process technology. The total number of correction parameters required for calibration is dependent on the interleaving ratio, M. To adapt the "Split-ADC" method to a TI system, 2M+1 half-sized converters are required to estimate 3(2M+1) correction parameters. This thesis presents a 4:1 "Split-TI" converter that achieves full convergence in less than 400,000 samples. The SAR architecture employs a binary weight capacitor array to convert analog inputs into digital output codes. Mismatch in the capacitor weights results in non-linear distortion error. By adding redundant bits and dividing the array into individual unit capacitors, the "Split-SAR" method can estimate the mismatch and correct the digital output code. The results from this work show a reduction in the non-linear distortion with the ability to converge in less than 750,000 samples.
Book Synopsis A 16 Bit 500KSps Low Power Successive Approximation Analog to Digital Converter by : Kun Yang
Download or read book A 16 Bit 500KSps Low Power Successive Approximation Analog to Digital Converter written by Kun Yang and published by . This book was released on 2009 with total page 61 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis A 12-bit 10-MS/s Calibration-Free Successive-Approximation Analog-to-Digital Converter by : 張力仁
Download or read book A 12-bit 10-MS/s Calibration-Free Successive-Approximation Analog-to-Digital Converter written by 張力仁 and published by . This book was released on 2019 with total page 115 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis A Study of Capacitor Array Calibration for a Successive Approximation Analog-to-digital Converter by : Ji Ma
Download or read book A Study of Capacitor Array Calibration for a Successive Approximation Analog-to-digital Converter written by Ji Ma and published by . This book was released on 2013 with total page 110 pages. Available in PDF, EPUB and Kindle. Book excerpt: Analog-to-digital converters (ADCs) are driven by rapid development of mobile communication systems to have higher speed, higher resolution and lower power consumption. Among multiple ADC architectures, successive approximation (SAR) ADCs attract great attention in mixed-signal design community recently. It is due to the fact that they do not contain amplification components and the digital logics are scaling friendly. Therefore, it is easier to design a SAR ADC with smaller component size in advanced technology than other ADC architectures, which decreases the power consumption and increases the speed of the circuit. However, capacitor mismatch limits the minimum size of unit capacitors which could be used for a SAR ADC with more than 10 bit resolution. Large capacitor both limits conversion speed and increases switching power. In this design project, a novel switching scheme and a novel calibration method are adopted to overcome the capacitor mismatch constraint. The switching scheme uses monotonic switching in a SAR ADC to gain one extra bit, and switches a dummy capacitor between the common mode voltage level (Vcm) and the ground (gnd) to obtain another extra bit. To keep the resolution constant, the capacitor number is reduced by two. The calibration method extracts missing code width to estimate the actual value of capacitors. The missing code extraction is accomplished by detecting metastable state of a comparator, forcing the current bit value and using less significant bits to measure the actual capacitor value. Dither method is adopted to improve calibration accuracy. Behavior model simulation is provided to verify the effectiveness of the calibration method. A circuit design of a 12 bit ADC and the simulation for schematic design is presented in this report.
Book Synopsis A Digital Calibration Technique with Recursive Discrete Fourier Transform for Successive-Approximation Analog-to-Digital Converters by : 阮翌翔
Download or read book A Digital Calibration Technique with Recursive Discrete Fourier Transform for Successive-Approximation Analog-to-Digital Converters written by 阮翌翔 and published by . This book was released on 2016 with total page 88 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis A Fast-Fourier-Transform-Based Digital Calibration Technique for Successive-Approximation-Register Analog-to-Digital Converters by : 李育丞
Download or read book A Fast-Fourier-Transform-Based Digital Calibration Technique for Successive-Approximation-Register Analog-to-Digital Converters written by 李育丞 and published by . This book was released on 2018 with total page 81 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis Digitally Calibrated Analog-to-digital Converters in Deep Sub-micron CMOS by : Cheongyuen William Tsang
Download or read book Digitally Calibrated Analog-to-digital Converters in Deep Sub-micron CMOS written by Cheongyuen William Tsang and published by . This book was released on 2008 with total page 380 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis Methodology for the Digital Calibration of Analog Circuits and Systems by : Marc Pastre
Download or read book Methodology for the Digital Calibration of Analog Circuits and Systems written by Marc Pastre and published by Springer Science & Business Media. This book was released on 2006-01-17 with total page 269 pages. Available in PDF, EPUB and Kindle. Book excerpt: Methodology for the Digital Calibration of Analog Circuits and Systems shows how to relax the extreme design constraints in analog circuits, allowing the realization of high-precision systems even with low-performance components. A complete methodology is proposed, and three applications are detailed. To start with, an in-depth analysis of existing compensation techniques for analog circuit imperfections is carried out. The M/2+M sub-binary digital-to-analog converter is thoroughly studied, and the use of this very low-area circuit in conjunction with a successive approximations algorithm for digital compensation is described. A complete methodology based on this compensation circuit and algorithm is then proposed. The detection and correction of analog circuit imperfections is studied, and a simulation tool allowing the transparent simulation of analog circuits with automatic compensation blocks is introduced. The first application shows how the sub-binary M/2+M structure can be employed as a conventional digital-to-analog converter if two calibration and radix conversion algorithms are implemented. The second application, a SOI 1T DRAM, is then presented. A digital algorithm chooses a suitable reference value that compensates several circuit imperfections together, from the sense amplifier offset to the dispersion of the memory read currents. The third application is the calibration of the sensitivity of a current measurement microsystem based on a Hall magnetic field sensor. Using a variant of the chopper modulation, the spinning current technique, combined with a second modulation of a reference signal, the sensitivity of the complete system is continuously measured without interrupting normal operation. A thermal drift lower than 50 ppm/°C is achieved, which is 6 to 10 times less than in state-of-the-art implementations. Furthermore, the calibration technique also compensates drifts due to mechanical stresses and ageing.
Book Synopsis Analog-digital Conversion Handbook by : Barbara W. Stephenson
Download or read book Analog-digital Conversion Handbook written by Barbara W. Stephenson and published by . This book was released on 1964 with total page 88 pages. Available in PDF, EPUB and Kindle. Book excerpt:
