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Author :
Publisher :
ISBN 13 :
Total Pages : 326 pages
Book Rating : 4.:/5 (931 download)
Download or read book Fault Tolerant Topologies and Routing Algorithms for Efficient Networks Design written by and published by . This book was released on 2010 with total page 326 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Author : Anas Hamdi Abu Taleb
Publisher :
ISBN 13 :
Total Pages : pages
Book Rating : 4.:/5 (16 download)
Download or read book Fault Tolerant Topologies and Routing Algorithms for Efficient Sensor Networks Design written by Anas Hamdi Abu Taleb and published by . This book was released on 2010 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt:
Author : Maurizio Palesi
Publisher : Springer Science & Business Media
ISBN 13 : 1461482747
Total Pages : 411 pages
Book Rating : 4.4/5 (614 download)
Download or read book Routing Algorithms in Networks-on-Chip written by Maurizio Palesi and published by Springer Science & Business Media. This book was released on 2013-10-22 with total page 411 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book provides a single-source reference to routing algorithms for Networks-on-Chip (NoCs), as well as in-depth discussions of advanced solutions applied to current and next generation, many core NoC-based Systems-on-Chip (SoCs). After a basic introduction to the NoC design paradigm and architectures, routing algorithms for NoC architectures are presented and discussed at all abstraction levels, from the algorithmic level to actual implementation. Coverage emphasizes the role played by the routing algorithm and is organized around key problems affecting current and next generation, many-core SoCs. A selection of routing algorithms is included, specifically designed to address key issues faced by designers in the ultra-deep sub-micron (UDSM) era, including performance improvement, power, energy, and thermal issues, fault tolerance and reliability.
Author : David Scott Moore
Publisher :
ISBN 13 :
Total Pages : 70 pages
Book Rating : 4.:/5 (169 download)
Download or read book Fault Tolerant Design Algorithms for Common Network Topologies written by David Scott Moore and published by . This book was released on 1987 with total page 70 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Author : Srinivasan Murali
Publisher : Springer Science & Business Media
ISBN 13 : 1402097573
Total Pages : 200 pages
Book Rating : 4.4/5 (2 download)
Download or read book Designing Reliable and Efficient Networks on Chips written by Srinivasan Murali and published by Springer Science & Business Media. This book was released on 2009-05-26 with total page 200 pages. Available in PDF, EPUB and Kindle. Book excerpt: Developing NoC based interconnect tailored to a particular application domain, satisfying the application performance constraints with minimum power-area overhead is a major challenge. With technology scaling, as the geometries of on-chip devices reach the physical limits of operation, another important design challenge for NoCs will be to provide dynamic (run-time) support against permanent and intermittent faults that can occur in the system. The purpose of Designing Reliable and Efficient Networks on Chips is to provide state-of-the-art methods to solve some of the most important and time-intensive problems encountered during NoC design.
Author : Ajith Abraham
Publisher : Springer
ISBN 13 : 3030166570
Total Pages : 1158 pages
Book Rating : 4.0/5 (31 download)
Download or read book Intelligent Systems Design and Applications written by Ajith Abraham and published by Springer. This book was released on 2019-04-11 with total page 1158 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book highlights recent research on Intelligent Systems and Nature Inspired Computing. It presents 212 selected papers from the 18th International Conference on Intelligent Systems Design and Applications (ISDA 2018) and the 10th World Congress on Nature and Biologically Inspired Computing (NaBIC), which was held at VIT University, India. ISDA-NaBIC 2018 was a premier conference in the field of Computational Intelligence and brought together researchers, engineers and practitioners whose work involved intelligent systems and their applications in industry and the “real world.” Including contributions by authors from over 40 countries, the book offers a valuable reference guide for all researchers, students and practitioners in the fields of Computer Science and Engineering.
Author : Aniruddha S. Vaidya
Publisher :
ISBN 13 :
Total Pages : 20 pages
Book Rating : 4.:/5 (39 download)
Download or read book A Testbed for Evaluation of Fault-tolerant Routing in Multiprocessor Interconnection Networks written by Aniruddha S. Vaidya and published by . This book was released on 1998 with total page 20 pages. Available in PDF, EPUB and Kindle. Book excerpt: Abstract: "With parallel machines increasingly taking on critical and complex applications, it is important to make them dependable to ensure their commercial success. Fault-tolerance in the network to accommodate link and node failures is an important step towards this goal. This can be achieved by employing cost-effective fault-tolerant algorithms. However, despite substantial efforts on the theoretical front in developing fault-tolerant routing techniques and architectures, these ideas have not manifested themselves in many commercial platforms. The ramifications of providing fault-tolerant routing in terms of cost and performance is still not clear to the computer architect. Such an insight can only be gained through detailed analysis of a design with realistic workloads. Since no current evaluation platform supports this, previous research on fault-tolerant routing has used synthetic workloads for analyzing performance. This paper presents a comprehensive evaluation testbed for interconnection networks and routing algorithms using real applications. The testbed is flexible enough to implement any network topology and fault-tolerant routing algorithm, and allows the system architect to study the cost versus performance tradeoffs for a range of network parameters. We illustrate its use with one fault-tolerant algorithm and analyze the performance of four shared memory applications with different fault conditions. We also show how the testbed can be used to drive future research in fault-tolerant routing algorithms and architectures, by proposing and evaluating novel architectural enhancements to the network router, called path selection heuristics (PSH). We propose three such schemes and the Least Recently Used (LRU) PSH is shown to give the best performance in the presence of faults."
Author : Xiaowei Li
Publisher : Springer Nature
ISBN 13 : 9811985510
Total Pages : 318 pages
Book Rating : 4.8/5 (119 download)
Download or read book Built-in Fault-Tolerant Computing Paradigm for Resilient Large-Scale Chip Design written by Xiaowei Li and published by Springer Nature. This book was released on 2023-03-01 with total page 318 pages. Available in PDF, EPUB and Kindle. Book excerpt: With the end of Dennard scaling and Moore’s law, IC chips, especially large-scale ones, now face more reliability challenges, and reliability has become one of the mainstay merits of VLSI designs. In this context, this book presents a built-in on-chip fault-tolerant computing paradigm that seeks to combine fault detection, fault diagnosis, and error recovery in large-scale VLSI design in a unified manner so as to minimize resource overhead and performance penalties. Following this computing paradigm, we propose a holistic solution based on three key components: self-test, self-diagnosis and self-repair, or “3S” for short. We then explore the use of 3S for general IC designs, general-purpose processors, network-on-chip (NoC) and deep learning accelerators, and present prototypes to demonstrate how 3S responds to in-field silicon degradation and recovery under various runtime faults caused by aging, process variations, or radical particles. Moreover, we demonstrate that 3S not only offers a powerful backbone for various on-chip fault-tolerant designs and implementations, but also has farther-reaching implications such as maintaining graceful performance degradation, mitigating the impact of verification blind spots, and improving chip yield. This book is the outcome of extensive fault-tolerant computing research pursued at the State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences over the past decade. The proposed built-in on-chip fault-tolerant computing paradigm has been verified in a broad range of scenarios, from small processors in satellite computers to large processors in HPCs. Hopefully, it will provide an alternative yet effective solution to the growing reliability challenges for large-scale VLSI designs.
Author : Érika Cota
Publisher : Springer Science & Business Media
ISBN 13 : 1461407915
Total Pages : 220 pages
Book Rating : 4.4/5 (614 download)
Download or read book Reliability, Availability and Serviceability of Networks-on-Chip written by Érika Cota and published by Springer Science & Business Media. This book was released on 2011-09-23 with total page 220 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book presents an overview of the issues related to the test, diagnosis and fault-tolerance of Network on Chip-based systems. It is the first book dedicated to the quality aspects of NoC-based systems and will serve as an invaluable reference to the problems, challenges, solutions, and trade-offs related to designing and implementing state-of-the-art, on-chip communication architectures.
Author : Abdulaziz Alhussien
Publisher :
ISBN 13 : 9781303167805
Total Pages : 137 pages
Book Rating : 4.1/5 (678 download)
Download or read book Design and Development of Reliable and Fault-tolerant Network-on-chip Router Architecture written by Abdulaziz Alhussien and published by . This book was released on 2013 with total page 137 pages. Available in PDF, EPUB and Kindle. Book excerpt: Networks on Chip (NoC) systems have been proposed as potential solutions for the interconnect demands in multi-processor System-on-Chip (MPSoC) environments. With the increase in the number of transistors on-chip and as CMOS technology scales down to nano technology, electronic components and interconnects are vulnerable to the effects of radiation, temperature variations and fabrication defects. The reliability of interconnection networks becomes a critical design factor. This has led to the design and the development of robust and fault-tolerant architectures. This dissertation addresses some of the key challenges in designing fault-tolerant NoC systems. Fault-tolerant adaptive routing algorithms for 2D mesh NoC architectures are proposed. The new adaptive routing algorithms for NePA architecture are able to tolerate faults in links in the NoC by rerouting packets in a proper alternative direction. The required hardware and software extensions are discussed and the performance of the router design is evaluated. The performance and its hardware complexity of the router demonstrate the feasibility of providing fault-tolerance design for NoC. Moreover, deadlock and livelock situations affect the functionality and the performance of NoC platforms. Thus. this dissertation considers these challenges as well when developing routing algorithms. The routing algorithms are verified to provide low overhead performance while ensuring deadlock/livelock freedom. This dissertation also proposes fault-tolerant routing algorithms for high throughput Diagonal Mesh NePA (DMesh) NoC. The routing algorithms are optimized to achieve efficient performance and low cost overhead while maintaining the correctness and deadlock/livelock freedom. To achieve high performance computing, hundreds of cores are integrated inside a chip. As cores and interconnections run synchronously at certain frequencies, Electromagnetic Interference (EMI) becomes very high and may affect the electronic circuits and therefore generate faults. An asynchronous NoC chip that is based on delay-insistent logic is proposed. Performance evaluation has demonstrated the proposed approach as a solution to implement Globally Asynchronous/Locally synchronous (GALS) architectures.
Author : Jimson Mathew
Publisher : Springer Science & Business Media
ISBN 13 : 1461441935
Total Pages : 347 pages
Book Rating : 4.4/5 (614 download)
Download or read book Energy-Efficient Fault-Tolerant Systems written by Jimson Mathew and published by Springer Science & Business Media. This book was released on 2013-09-07 with total page 347 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book describes the state-of-the-art in energy efficient, fault-tolerant embedded systems. It covers the entire product lifecycle of electronic systems design, analysis and testing and includes discussion of both circuit and system-level approaches. Readers will be enabled to meet the conflicting design objectives of energy efficiency and fault-tolerance for reliability, given the up-to-date techniques presented.
Author : Konstantinos Tatas
Publisher : Springer Science & Business Media
ISBN 13 : 1461442745
Total Pages : 271 pages
Book Rating : 4.4/5 (614 download)
Download or read book Designing 2D and 3D Network-on-Chip Architectures written by Konstantinos Tatas and published by Springer Science & Business Media. This book was released on 2013-10-08 with total page 271 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book covers key concepts in the design of 2D and 3D Network-on-Chip interconnect. It highlights design challenges and discusses fundamentals of NoC technology, including architectures, algorithms and tools. Coverage focuses on topology exploration for both 2D and 3D NoCs, routing algorithms, NoC router design, NoC-based system integration, verification and testing, and NoC reliability. Case studies are used to illuminate new design methodologies.
Author : Yan Zhang
Publisher : IGI Global
ISBN 13 : 1599049007
Total Pages : 860 pages
Book Rating : 4.5/5 (99 download)
Download or read book Handbook of Research on Wireless Security written by Yan Zhang and published by IGI Global. This book was released on 2008-01-01 with total page 860 pages. Available in PDF, EPUB and Kindle. Book excerpt: Provides research on security issues in various wireless communications, recent advances in wireless security, the wireless security model, and future directions in wireless security.
Author : Masaru Fukushi
Publisher :
ISBN 13 :
Total Pages : 0 pages
Book Rating : 4.:/5 (139 download)
Download or read book A Novel Approach for the Design of Fault-Tolerant Routing Algorithms in NoCs written by Masaru Fukushi and published by . This book was released on 2019 with total page 0 pages. Available in PDF, EPUB and Kindle. Book excerpt: Due to the faults in system fabrication and run time, designing an efficient fault-tolerant routing algorithm with the property of deadlock-freeness is crucial for realizing dependable Network-on-Chip (NoC) systems with high communication performance. In this chapter, we introduce a novel approach for the design of fault-tolerant routing algorithms in NoCs. The common idea of the fault-tolerant routing has been undoubtedly to detour faulty nodes, while our approach allows passing through faulty nodes with the slight modification of NoC architecture. As a design example, we present an XY-based routing algorithm with the passage function. To investigate the effect of the approach, we compare the communication performance (i.e. average latency) of the XY-based algorithm with well-known region-based algorithms under the condition of with and without virtual channels. Finally, we provide possible directions of future research on the fault-tolerant routing with the passage function.
Author : Muhammad Athar Javed Sethi
Publisher : CRC Press
ISBN 13 : 100004811X
Total Pages : 158 pages
Book Rating : 4.0/5 ( download)
Download or read book Bio-Inspired Fault-Tolerant Algorithms for Network-on-Chip written by Muhammad Athar Javed Sethi and published by CRC Press. This book was released on 2020-03-17 with total page 158 pages. Available in PDF, EPUB and Kindle. Book excerpt: Network on Chip (NoC) addresses the communication requirement of different nodes on System on Chip. The bio-inspired algorithms improve the bandwidth utilization, maximize the throughput and reduce the end-to-end latency and inter-flit arrival time. This book exclusively presents in-depth information regarding bio-inspired algorithms solving real world problems focussing on fault-tolerant algorithms inspired by the biological brain and implemented on NoC. It further documents the bio-inspired algorithms in general and more specifically, in the design of NoC. It gives an exhaustive review and analysis of the NoC architectures developed during the last decade according to various parameters. Key Features: Covers bio-inspired solutions pertaining to Network-on-Chip (NoC) design solving real world examples Includes bio-inspired NoC fault-tolerant algorithms with detail coding examples Lists fault-tolerant algorithms with detailed examples Reviews basic concepts of NoC Discusses NoC architectures developed-to-date
Author : Mohammad Ilyas
Publisher : CRC Press
ISBN 13 : 0203489632
Total Pages : 864 pages
Book Rating : 4.2/5 (34 download)
Download or read book Handbook of Sensor Networks written by Mohammad Ilyas and published by CRC Press. This book was released on 2004-07-28 with total page 864 pages. Available in PDF, EPUB and Kindle. Book excerpt: As the field of communications networks continues to evolve, the challenging area of wireless sensor networks is rapidly coming of age. Recent advances have made it possible to make sensor components more compact, robust, and energy efficient than ever, earning the idiosyncratic alias ofSmart Dust. Production has also improved, yielding larger,
Author : Isiaka Alimi
Publisher : BoD – Books on Demand
ISBN 13 : 1839681489
Total Pages : 111 pages
Book Rating : 4.8/5 (396 download)
Download or read book Network-on-Chip written by Isiaka Alimi and published by BoD – Books on Demand. This book was released on 2022-04-06 with total page 111 pages. Available in PDF, EPUB and Kindle. Book excerpt: Limitations of bus-based interconnections related to scalability, latency, bandwidth, and power consumption for supporting the related huge number of on-chip resources result in a communication bottleneck. These challenges can be efficiently addressed with the implementation of a network-on-chip (NoC) system. This book gives a detailed analysis of various on-chip communication architectures and covers different areas of NoCs such as potentials, architecture, technical challenges, optimization, design explorations, and research directions. In addition, it discusses current and future trends that could make an impactful and meaningful contribution to the research and design of on-chip communications and NoC systems.
