Energy Efficient Successive Approximation Analog To Digital Converter

Author : Muhammad Ahmadi
Publisher :
ISBN 13 :
Total Pages : 144 pages
Book Rating : 4.:/5 (923 download)

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Download or read book Comparator Power Reduction for Low Power Successive Approximation Analog to Digital Converters written by Muhammad Ahmadi and published by . This book was released on 2015 with total page 144 pages. Available in PDF, EPUB and Kindle. Book excerpt: Many applications like sensor nodes, wireless communications and consumer products require analog-to-digital converters (ADCs) to digitize the analog information. Charge redistribution successive approximation register (SAR) ADC has been a popular candidate in these applications due to its simplicity, low power consumption, medium speed and resolution. The three primary components of a SAR ADC are the digital-to-analog converter (DAC), digital SAR logic, and comparator. The power consumption of the DAC can be greatly minimized by employing a small unit capacitor and digital circuits benefit from technology scaling. Consequently, the comparator has become a major source of power consumption in recent power efficient SAR ADCs. Two comparator power reduction techniques are proposed which are based on the observation that the comparator noise variance need not be the same for each bit cycle of the SAR ADC. So, the performance of the SAR ADC is analyzed rigorously assuming that the comparator thermal noise differs for each bit cycle. The mathematical model suggests that using the same comparator noise variance for each bit cycle is suboptimal and results in more power consumption than necessary. As a first technique, a noise programmable comparator based on majority vote technique is proposed to adjust the comparator noise performance at each bit step by changing the number of votes taken at each bit step. As a proof of concept, a 10b SAR ADC that operates at 0.5 V supply voltage and supports a flexible differential input dynamic range from 0.4 V to 1 V has been fabricated in 65nm CMOS process. Second, the optimal comparators that need to be used to achieve a desired overall performance at minimum power levels are theoretically analyzed. Simulation results show that up to 50% and 60% reduction in comparator power consumption for 10b and 12b SAR ADCs, respectively, can be achieved. To reduce the implementation complexity, the comparator noise allocation problem is also solved when fewer than N comparators are employed in an N-bit SAR ADC. Simulation results suggest that two comparators are sufficient to achieve near ideal performance.