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Digital Self Calibration Techniques For High Accuracy High Speed Analog To Digital Converters
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Book Synopsis Digital Self-calibration Techniques for High-accuracy, High Speed Analog-to-digital Converters by : Andrew Nicholas Karanicolas
Download or read book Digital Self-calibration Techniques for High-accuracy, High Speed Analog-to-digital Converters written by Andrew Nicholas Karanicolas and published by . This book was released on 1994 with total page 448 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis Digital Self-calibration Techniques for High-accuracy, High-speed Analog-to-digital Converters by : Andrew Nicolas Karanicolas
Download or read book Digital Self-calibration Techniques for High-accuracy, High-speed Analog-to-digital Converters written by Andrew Nicolas Karanicolas and published by . This book was released on 1994 with total page 448 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis Low-Power High-Resolution Analog to Digital Converters by : Amir Zjajo
Download or read book Low-Power High-Resolution Analog to Digital Converters written by Amir Zjajo and published by Springer Science & Business Media. This book was released on 2010-10-29 with total page 311 pages. Available in PDF, EPUB and Kindle. Book excerpt: With the fast advancement of CMOS fabrication technology, more and more signal-processing functions are implemented in the digital domain for a lower cost, lower power consumption, higher yield, and higher re-configurability. This has recently generated a great demand for low-power, low-voltage A/D converters that can be realized in a mainstream deep-submicron CMOS technology. However, the discrepancies between lithography wavelengths and circuit feature sizes are increasing. Lower power supply voltages significantly reduce noise margins and increase variations in process, device and design parameters. Consequently, it is steadily more difficult to control the fabrication process precisely enough to maintain uniformity. The inherent randomness of materials used in fabrication at nanoscopic scales means that performance will be increasingly variable, not only from die-to-die but also within each individual die. Parametric variability will be compounded by degradation in nanoscale integrated circuits resulting in instability of parameters over time, eventually leading to the development of faults. Process variation cannot be solved by improving manufacturing tolerances; variability must be reduced by new device technology or managed by design in order for scaling to continue. Similarly, within-die performance variation also imposes new challenges for test methods. In an attempt to address these issues, Low-Power High-Resolution Analog-to-Digital Converters specifically focus on: i) improving the power efficiency for the high-speed, and low spurious spectral A/D conversion performance by exploring the potential of low-voltage analog design and calibration techniques, respectively, and ii) development of circuit techniques and algorithms to enhance testing and debugging potential to detect errors dynamically, to isolate and confine faults, and to recover errors continuously. The feasibility of the described methods has been verified by measurements from the silicon prototypes fabricated in standard 180nm, 90nm and 65nm CMOS technology.
Book Synopsis Background Digital Calibration Techniques for High-speed, High Resolution Analog-to-digital Data Converters by : Yun-Shiang Shu
Download or read book Background Digital Calibration Techniques for High-speed, High Resolution Analog-to-digital Data Converters written by Yun-Shiang Shu and published by . This book was released on 2008 with total page 111 pages. Available in PDF, EPUB and Kindle. Book excerpt: A high-speed, high-resolution analog-to-digital converter (ADC) is a key component in broadband communication transceivers, video imaging systems, and instrumentation. As the ADC speed increases with the advances in IC fabrication technology, the ADC resolution is still limited by the non-ideal effects of the circuits, such as device inaccuracy, component mismatch, and finite device gain. A recent trend for enhancing the resolution is to calibrate the non-ideal effects in background with the aid of digital signal processing. These techniques are preferred since the calibration accuracy is not limited by the accuracy of the analog components, and the calibration tracks the variations of process, voltage and temperature without interrupting ADC's normal operation. This dissertation describes the background calibration techniques for three high-speed, high-resolution ADCs using different architectures: pipelined, floating-point, and continuous-time (CT) [delta]-[sigma]. For pipelined ADCs, a background digital calibration technique with signal-dependent dithering scheme is proposed to overcome the dither magnitude and measurement time constraints with the existing fixed-magnitude dithering. A 15-b, 20-MS/s prototype ADC achieves a spurious-free dynamic range (SFDR) of 98 dB and a peak signal-to-noise plus distortion ratio (SNDR) of 73 dB. The chip is fabricated in 0.18-um complementary metal-oxide-semiconductor (CMOS) process, occupies an active area of 2.3 x 1.7 mm2, and consumes 285 mW at 1.8 V. The concept of signal-dependent dithering is also applied to a floating-point ADC (FADC) to calibrate the gain and offset errors in the variable gain amplifier (VGA) stages. A digitally-calibrated 10~15-b 60-MS/s FADC adjusts its quantization steps instantly depending on the sampled input level and enhances the integral non-linearity (INL) from 24 to 0.9 least significant bit (LSB) at a 15-b level for small input signals. The chip is fabricated in 0.18-um CMOS process, occupies 3.5 x 2.5 mm2, and consumes 300 mW at 1.8 V. In the CT [delta]-[sigma] architecture, the active filter is calibrated by injecting a binary pulse dither and nulling it with an LMS algorithm. The proposed technique calibrates the filter time-constant continuously with crystal accuracy, while the conventional master-slave approaches use additional analog components which limit the calibration accuracy. A 3rd-order 4-b prototype in 65-nm CMOS occupies 0.5 mm2 and consumes 50 mW at 1.3 V. It achieves a dynamic range (DR) of 81 dB over an 8-MHz signal bandwidth with a 2.4 Vpp full-scale range. Signal-to-noise ratio (SNR) and SNDR at -1 dBFS are 76 and 70 dB, respectively.
Book Synopsis Error Modeling, Self-calibration and Design of Pipelined Analog to Digital Converters by : Eric Georges Soenen
Download or read book Error Modeling, Self-calibration and Design of Pipelined Analog to Digital Converters written by Eric Georges Soenen and published by . This book was released on 1992 with total page 456 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis Analog Self-calibration Methods for Pipelined ADC by : Yvette Phan Ly Lee
Download or read book Analog Self-calibration Methods for Pipelined ADC written by Yvette Phan Ly Lee and published by . This book was released on 1999 with total page 182 pages. Available in PDF, EPUB and Kindle. Book excerpt: A large number of analog-to-digital converters (ADC) are used in transmission, switching, storage, and processing of voice, data, and video information in data communication systems. High speed and high-resolution ADC's are in increasing demand due to emerging telecommunication systems. Pipelined ADC's have the advantage of good speed, modest area and attractive power consumption over other ADC's. However, component mismatches have limited the accuracy of this type of ADC. Comparator offsets, offsets and gain errors of gain amplifiers, and digital-to-analog converter (DAC) errors contribute to non-linearity in pipelined ADC. In this thesis, two methods for self-calibrating pipelined ADC's in analog domain are presented. In one method, each of these non-idealities in a pipeline stage is corrected to give close to ideal transfer characteristic. Techniques for calibrating comparator offset, gain error, and DAC errors are proposed. Analyses show that a gain of better than 15-bit accuracy is achievable with 5 mV amplifier and comparator offsets, and 0.5% error in the common-mode voltage of the references. The second method for calibrating pipelined ADC involves the use of an algorithm for adjusting the DAC output levels in each pipeline stage. For calibration, adjustable DAC's and registers for storing the digital inputs of the calibrated DAC are required for each stage in the pipelined ADC. An additional comparator and a digital counter are also required for calibrating the DAC's and these components can be shared between stages. MatLab simulation is presented for a 14-bit, 1-bit-per-stage pipelined ADC. Random errors of maximum of ± 1% were introduced to the gains of the gain amplifiers and DAC output levels and random offset voltages of maximum ± 1 mV were introduced to the comparators. The calibrated ADC has INL and DNL within ± 1/2V [Subscript LSB].
Book Synopsis Digitally Assisted Techniques for Nyquist Rate Analog-to-Digital Converters by : Rabeeh Majidi
Download or read book Digitally Assisted Techniques for Nyquist Rate Analog-to-Digital Converters written by Rabeeh Majidi and published by . This book was released on 2015 with total page 204 pages. Available in PDF, EPUB and Kindle. Book excerpt: Abstract: With the advance of technology and rapid growth of digital systems, low power high speed analog-to- digital converters with great accuracy are in demand. To achieve high effective number of bits Analog-to-Digital Converter (ADC) calibration as a time consuming process is a potential bottleneck for designs. This dissertation presentsa fully digital background calibration algorithm for a 7- bit redundant flash ADC using split structure and look-up table based correction. Redundant comparators are used in the flash ADC design of this work in order to tolerate large offset voltages while minimizing signal input capacitance. The split ADC structure helps by eliminating the unknown input signal from the calibration path. The flash ADC has been designed in 180nm IBM CMOS technology and fabricated through MOSIS. This work was supported by Analog Devices, Wilmington, MA. While much research on ADC design has concentrated on increasing resolution and sample rate, there are many applications (e.g. biomedical devices and sensor networks) that do not require high performance but do require low power energy efficient ADCs. This dissertation also explores on design of a low quiescent current 100k Sps Successive Approximation (SAR) ADC that has been used as an error detection ADC for an automotive application in 350nm CD (CMOS-DMOS) technology. This work was supported by ON Semiconductor Corp, East Greenwich, RI.
Download or read book הגדה של פסח בית הבחירה written by and published by . This book was released on 1970 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis Reference-Free CMOS Pipeline Analog-to-Digital Converters by : Michael Figueiredo
Download or read book Reference-Free CMOS Pipeline Analog-to-Digital Converters written by Michael Figueiredo and published by Springer Science & Business Media. This book was released on 2012-08-24 with total page 189 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book shows that digitally assisted analog to digital converters are not the only way to cope with poor analog performance caused by technology scaling. It describes various analog design techniques that enhance the area and power efficiency without employing any type of digital calibration circuitry. These techniques consist of self-biasing for PVT enhancement, inverter-based design for improved speed/power ratio, gain-of-two obtained by voltage sum instead of charge redistribution, and current-mode reference shifting instead of voltage reference shifting. Together, these techniques allow enhancing the area and power efficiency of the main building blocks of a multiplying digital-to-analog converter (MDAC) based stage, namely, the flash quantizer, the amplifier, and the switched capacitor network of the MDAC. Complementing the theoretical analyses of the various techniques, a power efficient operational transconductance amplifier is implemented and experimentally characterized. Furthermore, a medium-low resolution reference-free high-speed time-interleaved pipeline ADC employing all mentioned design techniques and circuits is presented, implemented and experimentally characterized. This ADC is said to be reference-free because it precludes any reference voltage, therefore saving power and area, as reference circuits are not necessary. Experimental results demonstrate the potential of the techniques which enabled the implementation of area and power efficient circuits.
Book Synopsis Digital Background Calibration Techniques for Current-steering Digital-to-analog Converters by : Jenny Kuo
Download or read book Digital Background Calibration Techniques for Current-steering Digital-to-analog Converters written by Jenny Kuo and published by . This book was released on 2011 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: Current-steering (CS) digital-to-analog converters (DACs) are typically used for high-speed, high-accuracy applications since they are the fastest DAC architecture available that also can achieve relatively high resolution and linearity. However, as the performance specifications for both speed and accuracy in data converters continue to increase, circuit nonidealities are becoming more difficult to overcome using traditional analog design techniques. As a result, digital calibration has become an efficient and effective solution for designing high-performance DACs, where the advantages of process scaling can be fully exploited. Two digital background calibration techniques for CS DACs are presented in this thesis. The first technique improves the static linearity of a binary-weighted (BW) DAC by estimating and correcting for errors due to both mismatch and finite output resistance in the current sources, potentially allowing the DAC to be constructed with minimum size current sources. The errors are estimated with a slow-but-accurate reference analog-to-digital converter (Ref ADC) and a digital adaptive least-mean-squared algorithm. Correction is achieved using two auxiliary BW CS DACs: one for coarse correction and one for fine correction. Since the current source array of the DAC under calibration occupies a small area, gradient effects are small; however, these errors also can be overcome with the calibration described in this thesis. The dynamic performance of the DAC also improves with this calibration technique due to the reduced parasitics stemming from the reduced DAC area. Computer simulations demonstrate the effectiveness of the proposed technique for a 14-bit DAC operating at 100 MS/s. The second technique improves the dynamic linearity of a high-speed CS DAC. At high operating frequencies, the parasitic capacitors at the drain of the current sources dominate the finite output impedance of the DAC, causing input-dependent settling and memory errors. These errors introduce undesired frequency-dependent nonlinearities in the DAC output. The presented calibration technique estimates these errors with a slow-but-accurate Ref ADC and a digital adaptive recursive least-mean-squared algorithm. Correction is achieved using an auxiliary CS DAC. Computer simulations demonstrate the effectiveness of the proposed technique for a 12-bit DAC operating at 1 GS/s.
Book Synopsis Self-calibration Techniques for Successive Approximation Analog-to-digital Converters by : Hae-Seung Lee
Download or read book Self-calibration Techniques for Successive Approximation Analog-to-digital Converters written by Hae-Seung Lee and published by . This book was released on 1984 with total page 356 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis A Self Calibration Technique for Higher Order Incremental Analog to Digital Converters by : Donald C. Thelen (Jr.)
Download or read book A Self Calibration Technique for Higher Order Incremental Analog to Digital Converters written by Donald C. Thelen (Jr.) and published by . This book was released on 1996 with total page 276 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis Calibration and High Speed Techniques for CMOS Analog-to- Digital Converters by : Marco Macedo
Download or read book Calibration and High Speed Techniques for CMOS Analog-to- Digital Converters written by Marco Macedo and published by . This book was released on 2012 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: "The main focus of the work carried in this dissertation is to find the best design solution for an ultra high-speed Analog-to-Digital converter. Designing CMOS Analog-to-Digital converters in the gigahertz range for a good resolution is a challenge due to a lower power supply and smaller transistors. As a result, critical analog components (e.g., comparator, pre-amplifiers, band-gap) become more susceptible to process variation and make it hard to achieve a good resolution (e.g., higher than 6-bit). The traditional approach to design Analog-to-Digital converters does not work well with current CMOS technology and yields unpractical designs since it does not take advantage of the technology scaling down. For these reasons, this work investigates new designs topologies for the track-and-hold circuits needed at the front-end of ultra high-speed Analog-to- Digital converters and also investigates a digital foreground technique aimed at reducing the impact of process mismatch. For this purpose, two chips have been designed to investigate the best track-and-hold architecture based on a differential switch source-follower and to validate a proposed digital foreground calibration technique using resistive loads." --
Book Synopsis Calibration Techniques in Nyquist A/D Converters by : Hendrik van der Ploeg
Download or read book Calibration Techniques in Nyquist A/D Converters written by Hendrik van der Ploeg and published by Springer Science & Business Media. This book was released on 2006-09-13 with total page 203 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book analyses different A/D-converter architectures with an emphasis on the maximum achievable power efficiency. It also provides an accessible overview of the state-of-the art in calibration techniques for Nyquist A/D converters. The calibration techniques presented are applicable to other analog-to-digital systems, such as those applied in integrated receivers. They allow implementation without introducing a speed or power penalty.
Book Synopsis A Calibration Service for Analog-to-digital and Digital-to-analog Converters by : T. Michael Souders
Download or read book A Calibration Service for Analog-to-digital and Digital-to-analog Converters written by T. Michael Souders and published by . This book was released on 1981 with total page 84 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis Offset Reduction Techniques in High-Speed Analog-to-Digital Converters by : Pedro M. Figueiredo
Download or read book Offset Reduction Techniques in High-Speed Analog-to-Digital Converters written by Pedro M. Figueiredo and published by Springer. This book was released on 2010-10-28 with total page 0 pages. Available in PDF, EPUB and Kindle. Book excerpt: Offset Reduction Techniques in High-Speed Analog-to-Digital Converters analyzes, describes the design, and presents test results of Analog-to-Digital Converters (ADCs) employing the three main high-speed architectures: flash, two-step flash and folding and interpolation. The advantages and limitations of each one are reviewed, and the techniques employed to improve their performance are discussed.
Book Synopsis All Digital, Background Calibration for Time-Interleaved and Successive Approximation Register Analog-to-Digital Converters by : Christopher Leonidas David
Download or read book All Digital, Background Calibration for Time-Interleaved and Successive Approximation Register Analog-to-Digital Converters written by Christopher Leonidas David and published by . This book was released on 2010 with total page 370 pages. Available in PDF, EPUB and Kindle. Book excerpt: Abstract: The growth of digital systems underscores the need to convert analog information to the digital domain at high speeds and with great accuracy. Analog-to-Digital Converter (ADC) calibration is often a limiting factor, requiring longer calibration times to achieve higher accuracy. The goal of this dissertation is to perform a fully digital background calibration using an arbitrary input signal for A/D converters. The work presented here adapts the cyclic "Split-ADC" calibration method to the time interleaved (TI) and successive approximation register (SAR) architectures. The TI architecture has three types of linear mismatch errors: offset, gain and aperture time delay. By correcting all three mismatch errors in the digital domain, each converter is capable of operating at the fastest speed allowed by the process technology. The total number of correction parameters required for calibration is dependent on the interleaving ratio, M. To adapt the "Split-ADC" method to a TI system, 2M+1 half-sized converters are required to estimate 3(2M+1) correction parameters. This thesis presents a 4:1 "Split-TI" converter that achieves full convergence in less than 400,000 samples. The SAR architecture employs a binary weight capacitor array to convert analog inputs into digital output codes. Mismatch in the capacitor weights results in non-linear distortion error. By adding redundant bits and dividing the array into individual unit capacitors, the "Split-SAR" method can estimate the mismatch and correct the digital output code. The results from this work show a reduction in the non-linear distortion with the ability to converge in less than 750,000 samples.
