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Digital Background Calibration Techniques For Current Steering Digital To Analog Converters
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Book Synopsis Digital Background Calibration Techniques for Current-steering Digital-to-analog Converters by : Jenny Kuo
Download or read book Digital Background Calibration Techniques for Current-steering Digital-to-analog Converters written by Jenny Kuo and published by . This book was released on 2011 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: Current-steering (CS) digital-to-analog converters (DACs) are typically used for high-speed, high-accuracy applications since they are the fastest DAC architecture available that also can achieve relatively high resolution and linearity. However, as the performance specifications for both speed and accuracy in data converters continue to increase, circuit nonidealities are becoming more difficult to overcome using traditional analog design techniques. As a result, digital calibration has become an efficient and effective solution for designing high-performance DACs, where the advantages of process scaling can be fully exploited. Two digital background calibration techniques for CS DACs are presented in this thesis. The first technique improves the static linearity of a binary-weighted (BW) DAC by estimating and correcting for errors due to both mismatch and finite output resistance in the current sources, potentially allowing the DAC to be constructed with minimum size current sources. The errors are estimated with a slow-but-accurate reference analog-to-digital converter (Ref ADC) and a digital adaptive least-mean-squared algorithm. Correction is achieved using two auxiliary BW CS DACs: one for coarse correction and one for fine correction. Since the current source array of the DAC under calibration occupies a small area, gradient effects are small; however, these errors also can be overcome with the calibration described in this thesis. The dynamic performance of the DAC also improves with this calibration technique due to the reduced parasitics stemming from the reduced DAC area. Computer simulations demonstrate the effectiveness of the proposed technique for a 14-bit DAC operating at 100 MS/s. The second technique improves the dynamic linearity of a high-speed CS DAC. At high operating frequencies, the parasitic capacitors at the drain of the current sources dominate the finite output impedance of the DAC, causing input-dependent settling and memory errors. These errors introduce undesired frequency-dependent nonlinearities in the DAC output. The presented calibration technique estimates these errors with a slow-but-accurate Ref ADC and a digital adaptive recursive least-mean-squared algorithm. Correction is achieved using an auxiliary CS DAC. Computer simulations demonstrate the effectiveness of the proposed technique for a 12-bit DAC operating at 1 GS/s.
Book Synopsis Dynamic-Mismatch Mapping for Digitally-Assisted DACs by : Yongjian Tang
Download or read book Dynamic-Mismatch Mapping for Digitally-Assisted DACs written by Yongjian Tang and published by Springer Science & Business Media. This book was released on 2013-02-11 with total page 170 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book describes a novel digital calibration technique called dynamic-mismatch mapping (DMM) to improve the performance of digital to analog converters (DACs). Compared to other techniques, the DMM technique has the advantage of calibrating all mismatch errors without any noise penalty, which is particularly useful in order to meet the demand for high performance DACs in rapidly developing applications, such as multimedia and communication systems.
Book Synopsis Digital Background Calibration of Analog to Digital Converters by : Bahar Jalali-Farahani
Download or read book Digital Background Calibration of Analog to Digital Converters written by Bahar Jalali-Farahani and published by Springer. This book was released on 2013 with total page 200 pages. Available in PDF, EPUB and Kindle. Book excerpt: Digital Background Calibration of Analog to Digital Converters takes a deep look at the digital calibration techniques in analog-to-digital converters. The problem of compensating for analog circuits impairments is divided into a system identification problem and an error compensation problem. Different approaches in modelling the analog impairments are discussed. Although Digital Background Calibration of Analog to Digital Converters focuses on two popular types of ADCs mainly: Pipeline and Sigma Delta the techniques can be easily used for any analog and mixed-signal design. Design examples are provided that support the theory and show the application of these techniques in designing high performance data acquisitions systems for wireless communication systems, bio-implantable devices and space electronics.
Book Synopsis Digital Background Calibration Techniques for High-resolution, Wide Bandwidth Analog-to-digital Converters by : Alma Delic-Ibukic
Download or read book Digital Background Calibration Techniques for High-resolution, Wide Bandwidth Analog-to-digital Converters written by Alma Delic-Ibukic and published by . This book was released on 2008 with total page 368 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis Background Calibration of Time-Interleaved Data Converters by : Manar El-Chammas
Download or read book Background Calibration of Time-Interleaved Data Converters written by Manar El-Chammas and published by Springer Science & Business Media. This book was released on 2011-12-17 with total page 138 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book describes techniques for time-interleaving a number of analog-to-digital data converters to achieve demanding bandwidth requirements. Readers will benefit from the presentation of a low-power solution that can be used in actual products, while alleviating the time-varying signal artifacts that typically arise when implementing such a system architecture.
Book Synopsis Background Calibration Techniques for Analog-to-digital Converters in Scaled CMOS Technologies by : Kareem Abd-Elghani Ragab
Download or read book Background Calibration Techniques for Analog-to-digital Converters in Scaled CMOS Technologies written by Kareem Abd-Elghani Ragab and published by . This book was released on 2016 with total page 0 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis Calibration Techniques in Nyquist A/D Converters by : Hendrik van der Ploeg
Download or read book Calibration Techniques in Nyquist A/D Converters written by Hendrik van der Ploeg and published by Springer Science & Business Media. This book was released on 2006-09-13 with total page 203 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book analyses different A/D-converter architectures with an emphasis on the maximum achievable power efficiency. It also provides an accessible overview of the state-of-the art in calibration techniques for Nyquist A/D converters. The calibration techniques presented are applicable to other analog-to-digital systems, such as those applied in integrated receivers. They allow implementation without introducing a speed or power penalty.
Book Synopsis Background Digital Calibration Techniques for High-speed, High Resolution Analog-to-digital Data Converters by : Yun-Shiang Shu
Download or read book Background Digital Calibration Techniques for High-speed, High Resolution Analog-to-digital Data Converters written by Yun-Shiang Shu and published by . This book was released on 2008 with total page 111 pages. Available in PDF, EPUB and Kindle. Book excerpt: A high-speed, high-resolution analog-to-digital converter (ADC) is a key component in broadband communication transceivers, video imaging systems, and instrumentation. As the ADC speed increases with the advances in IC fabrication technology, the ADC resolution is still limited by the non-ideal effects of the circuits, such as device inaccuracy, component mismatch, and finite device gain. A recent trend for enhancing the resolution is to calibrate the non-ideal effects in background with the aid of digital signal processing. These techniques are preferred since the calibration accuracy is not limited by the accuracy of the analog components, and the calibration tracks the variations of process, voltage and temperature without interrupting ADC's normal operation. This dissertation describes the background calibration techniques for three high-speed, high-resolution ADCs using different architectures: pipelined, floating-point, and continuous-time (CT) [delta]-[sigma]. For pipelined ADCs, a background digital calibration technique with signal-dependent dithering scheme is proposed to overcome the dither magnitude and measurement time constraints with the existing fixed-magnitude dithering. A 15-b, 20-MS/s prototype ADC achieves a spurious-free dynamic range (SFDR) of 98 dB and a peak signal-to-noise plus distortion ratio (SNDR) of 73 dB. The chip is fabricated in 0.18-um complementary metal-oxide-semiconductor (CMOS) process, occupies an active area of 2.3 x 1.7 mm2, and consumes 285 mW at 1.8 V. The concept of signal-dependent dithering is also applied to a floating-point ADC (FADC) to calibrate the gain and offset errors in the variable gain amplifier (VGA) stages. A digitally-calibrated 10~15-b 60-MS/s FADC adjusts its quantization steps instantly depending on the sampled input level and enhances the integral non-linearity (INL) from 24 to 0.9 least significant bit (LSB) at a 15-b level for small input signals. The chip is fabricated in 0.18-um CMOS process, occupies 3.5 x 2.5 mm2, and consumes 300 mW at 1.8 V. In the CT [delta]-[sigma] architecture, the active filter is calibrated by injecting a binary pulse dither and nulling it with an LMS algorithm. The proposed technique calibrates the filter time-constant continuously with crystal accuracy, while the conventional master-slave approaches use additional analog components which limit the calibration accuracy. A 3rd-order 4-b prototype in 65-nm CMOS occupies 0.5 mm2 and consumes 50 mW at 1.3 V. It achieves a dynamic range (DR) of 81 dB over an 8-MHz signal bandwidth with a 2.4 Vpp full-scale range. Signal-to-noise ratio (SNR) and SNDR at -1 dBFS are 76 and 70 dB, respectively.
Book Synopsis Methodology for the Digital Calibration of Analog Circuits and Systems by : Marc Pastre
Download or read book Methodology for the Digital Calibration of Analog Circuits and Systems written by Marc Pastre and published by Springer. This book was released on 2009-09-03 with total page 254 pages. Available in PDF, EPUB and Kindle. Book excerpt: Methodology for the Digital Calibration of Analog Circuits and Systems shows how to relax the extreme design constraints in analog circuits, allowing the realization of high-precision systems even with low-performance components. A complete methodology is proposed, and three applications are detailed. To start with, an in-depth analysis of existing compensation techniques for analog circuit imperfections is carried out. The M/2+M sub-binary digital-to-analog converter is thoroughly studied, and the use of this very low-area circuit in conjunction with a successive approximations algorithm for digital compensation is described. A complete methodology based on this compensation circuit and algorithm is then proposed. The detection and correction of analog circuit imperfections is studied, and a simulation tool allowing the transparent simulation of analog circuits with automatic compensation blocks is introduced. The first application shows how the sub-binary M/2+M structure can be employed as a conventional digital-to-analog converter if two calibration and radix conversion algorithms are implemented. The second application, a SOI 1T DRAM, is then presented. A digital algorithm chooses a suitable reference value that compensates several circuit imperfections together, from the sense amplifier offset to the dispersion of the memory read currents. The third application is the calibration of the sensitivity of a current measurement microsystem based on a Hall magnetic field sensor. Using a variant of the chopper modulation, the spinning current technique, combined with a second modulation of a reference signal, the sensitivity of the complete system is continuously measured without interrupting normal operation. A thermal drift lower than 50 ppm/°C is achieved, which is 6 to 10 times less than in state-of-the-art implementations. Furthermore, the calibration technique also compensates drifts due to mechanical stresses and ageing.
Book Synopsis Nested Digital Background Calibration of a 12-bit Pipelined ADC Without an Input SHA by : Haoyue Wang
Download or read book Nested Digital Background Calibration of a 12-bit Pipelined ADC Without an Input SHA written by Haoyue Wang and published by . This book was released on 2008 with total page 220 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis Background Analog and Digital Calibration Techniques for Pipelined ADC's by : Sudipta Sarkar
Download or read book Background Analog and Digital Calibration Techniques for Pipelined ADC's written by Sudipta Sarkar and published by . This book was released on 2017 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: A digital background calibration technique to treat capacitor mismatch, residue gain error and nonlinearity in a pipelined analog-to-digital converter (ADC) based on the split-ADC architecture (J. McNeill et al., “Split ADC architecture for deterministic digital background calibration of a 16-bit 1-MS/s ADC,” IEEE J. of Solid-State Circuits, vol. 40, pp. 2437-2445, Dec. 2005) is reported. Although multiple works have been reported before on the split-calibration of pipelined analog-to-digital converters, none of them is comprehensive, i.e., capacitor mismatch, residue gain error and nonlinearity are never treated in one work at the same time. We, for the first time, recognize the multistage pipelined ADC with residue non-linearity calibration as a Nonlinear Least Squares problem. Behavioral simulation results demonstrate the efficacy of the technique, in which the signal-to-noise-and-distortion ratio (SNDR) and spurious-free-dynamic-range (SFDR) performance of a 15-bit split-pipelined ADC are improved from 42 dB and 50 dB to 88 dB and 102 dB on average, respectively. Secondly, an 8b, 1.3/1.39GS/s, 7/8.1mW two-step ADC is presented that introduces a single reference comparator based background comparator offset calibration technique. This work employs a dual-residue based inter-stage redundancy scheme to relax residue amplifier specifications (and enable high-speed operation at 0.85V supply) in a two-step ADC. Comparator offset calibration is implemented through body biasing with an area-efficient 8b offset calibration DAC. A prototype in 28nm Complementary Metal Oxide Semiconductor (CMOS) achieves 6.8 effective number of bits (ENOB) and 50fJ/c-s at DC and 6.3 ENOB and 68fJ/c-s at Nyquist, at a sample rate of 1.3GS/s. The measured SNDR/SFDR improve from 29.2/40.7dB to 42.6/57.7dB after calibration. The active area is 0.05mm2.
Book Synopsis Digital Background Calibration of Time-interleaved Analog-to-digital Converters by : Shafiq M. Jamal
Download or read book Digital Background Calibration of Time-interleaved Analog-to-digital Converters written by Shafiq M. Jamal and published by . This book was released on 2001 with total page 262 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis Background Digital Code-error Calibration of Analog-to-digital Converters by : Tzi-Hsiung Shu
Download or read book Background Digital Code-error Calibration of Analog-to-digital Converters written by Tzi-Hsiung Shu and published by . This book was released on 1994 with total page 152 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis Nested Digital Background Calibration of Pipelined Analog-to-digital Converters by : Xiaoyue Wang
Download or read book Nested Digital Background Calibration of Pipelined Analog-to-digital Converters written by Xiaoyue Wang and published by . This book was released on 2003 with total page 270 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis A Calibration Service for Analog-to-digital and Digital-to-analog Converters by : T. Michael Souders
Download or read book A Calibration Service for Analog-to-digital and Digital-to-analog Converters written by T. Michael Souders and published by . This book was released on 1981 with total page 84 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis Digital Background Calibration of Analog-to-digital Converters Using a Calibration Queue by : Ozan Ersan Erdoğan
Download or read book Digital Background Calibration of Analog-to-digital Converters Using a Calibration Queue written by Ozan Ersan Erdoğan and published by . This book was released on 1999 with total page 250 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis Split Calibration Techniques for Data Converters by : David Joseph Stoops
Download or read book Split Calibration Techniques for Data Converters written by David Joseph Stoops and published by . This book was released on 2014 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: Data converters are an instrumental part of modern day systems. As the bridge between the digital and analog domains, these converters are often a bottleneck. Therefore, their performance is of critical importance. Furthermore, the analog portions of data converters do not enjoy the benefits of scaling as much as digital circuits. In order to enhance analog performance and make full use of scaling in newer technologies, digital calibration algorithms have been developed to compensate for analog deficiencies using digital signal processing (DSP). This thesis expands on the split calibration procedure found in [1]-[8]. In particular, it will focus on a split [delta][sigma] modulator (DSM) and a split DAC. The split architecture makes use of two identical data converters, which form two channels, that operate with the same input, and generates an error signal from the their difference. This error signal is used in an LMS algorithm to digitally calibrate for the analog errors. The split DSM uses a wide-swing, low-distortion architecture from [9], with the MASH architecture. The split DSM model attempts to correct for DAC nonlinearity and coefficient mismatch of the MASH filter. However, a DSM is an inappropriate choice of data converter for reference calibration. A reference calibration is one in which the output is compared against a reference. The error that results from the difference in the output and the reference is used to adapt a digital model to correct for the error. The low resolution and correlation between output samples causes issues in an LMS style calibration. The split DAC makes use of two identical DACs, and examines their difference in the analog domain. It then uses a low resolution ADC to digitize the error signal. In the simplest case, the low resolution ADC is a single comparator, and the calibration reduces to a sign-LMS algorithm. This thesis presents a theoretical examination of this algorithm with circuit simulation results. A modified binary-weighted (BW), current steering (CS) DAC is examined. Simulation results show performance improvements for a 14-bit, 125MHz DAC.
