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Design Of Low Power Successive Approximation Register Analog To Digital Converter
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Book Synopsis Low-power Techniques for Successive Approximation Register (SAR) Analog-to-digital Converters by : Ramgopal Sekar
Download or read book Low-power Techniques for Successive Approximation Register (SAR) Analog-to-digital Converters written by Ramgopal Sekar and published by . This book was released on 2010 with total page 160 pages. Available in PDF, EPUB and Kindle. Book excerpt: In this work, the author investigated circuit techniques to reduce the power consumption of Successive Approximation Register Analog-to-Digital Converter (SAR-ADC). The author developed four low-power SAR-ADC design techniques, which are: (1) Low-power SAR-ADC design with split voltage reference, (2) Charge recycling techniques for low-power SAR-ADC design, (3) Low-power SAR-ADC design using two-capacitor arrays, (4) Power reduction techniques by dynamically minimizing SAR-ADC conversion cycles. Matlab simulations are performed to investigate the power saving by the proposed techniques. Simulation results show that significant power reduction can be achieved by using the developed techniques. In addition, design issues such as area overhead, design complexity associated with the proposed low-power techniques are also discussed in the thesis.
Book Synopsis Design of Low Power Successive Approximation Register Analog-to-Digital Converter by : Shu-I. Hu
Download or read book Design of Low Power Successive Approximation Register Analog-to-Digital Converter written by Shu-I. Hu and published by . This book was released on 2013 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis Design of High-performance and Low-power Successive Approximation Register (SAR) Analog-to-Digital Converter by : 蔡任桓
Download or read book Design of High-performance and Low-power Successive Approximation Register (SAR) Analog-to-Digital Converter written by 蔡任桓 and published by . This book was released on 2014 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis Data Conversion Handbook by : Walt Kester
Download or read book Data Conversion Handbook written by Walt Kester and published by Newnes. This book was released on 2005 with total page 977 pages. Available in PDF, EPUB and Kindle. Book excerpt: This complete update of a classic handbook originally created by Analog Devices and never previously published offers the most complete and up-to-date reference available on data conversion, from the world authority on the subject. It describes in depth the theory behind and the practical design of data conversion circuits. It describes the different architectures used in A/D and D/A converters - including many advances that have been made in this technology in recent years - and provides guidelines on which types are best suited for particular applications. It covers error characterization and testing specifications, essential design information that is difficult to find elsewhere. The book also contains a wealth of practical application circuits for interfacing and supporting A/D and D/A converters within an electronic system. In short, everything an electronics engineer needs to know about data converters can be found in this volume, making it an indispensable reference with broad appeal. The accompanying CD-ROM provides software tools for testing and analyzing data converters as well as a searchable pdf version of the text. * brings together a huge amount of information impossible to locate elsewhere. * many recent advances in converter technology simply aren't covered in any other book. * a must-have design reference for any electronics design engineer or technician
Book Synopsis Accelerated Successive Approximation Technique for Analog to Digital Converter Design by : Ram Harshvardhan Radhakrishnan
Download or read book Accelerated Successive Approximation Technique for Analog to Digital Converter Design written by Ram Harshvardhan Radhakrishnan and published by . This book was released on 2015 with total page 82 pages. Available in PDF, EPUB and Kindle. Book excerpt: This thesis work presents a novel technique to reduce the number of conversion cycles for Successive Approximation register (SAR) Analog to Digital Converters (ADC), thereby potentially improving the conversion speed as well as reducing its power consumption. Conventional SAR ADCs employ the binary search algorithm and they update only one bound, either the upper or lower bound, of the search space during one conversion cycle. The proposed method, referred to as the Accelerated-SAR or A-SAR, is capable of updating both the lower and upper bounds in a single conversion cycle. Even in cases that it can update only one bound, it does more aggressively. The proposed technique is implemented in a 10-bit SAR ADC circuit with 0.5V power supply and rail-to-rail input range. To cope with the ultra-low voltage design challenge, Time-to-Digital conversion techniques are used in the implementation. Important design issues are also discussed for the charge scaling array and Voltage Controlled Delay Lines (VCDL), which are important building blocks in the ADC implementation.
Book Synopsis A 16 Bit 500KSps Low Power Successive Approximation Analog to Digital Converter by : Kun Yang
Download or read book A 16 Bit 500KSps Low Power Successive Approximation Analog to Digital Converter written by Kun Yang and published by . This book was released on 2009 with total page 61 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis Successive-approximation-register Analog-to-digital-converter for Low-power CMOS Image Sensing and Compression by : Denis Guangyin Chen
Download or read book Successive-approximation-register Analog-to-digital-converter for Low-power CMOS Image Sensing and Compression written by Denis Guangyin Chen and published by . This book was released on 2013 with total page 134 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis Low-power Successive Approximation Analog to Digital Converter with Digital Calibration by : Wei Li
Download or read book Low-power Successive Approximation Analog to Digital Converter with Digital Calibration written by Wei Li and published by . This book was released on 2014 with total page 73 pages. Available in PDF, EPUB and Kindle. Book excerpt: IC designers are continuously facing the challenges from reduced CMOS feature sizes and supply voltages. ADCs that deliver satisfactory resolutions/speeds while utilizing the state-of-the-art technologies to save power are in high demand. The analog circuits are more and more assisted by various digital calibration techniques to get boosted performances. This dissertation is focused on a low-power 12-bit 12.5-MS/s successive approximation (SAR) ADC with a couple of calibration schemes. The performances of the proposed SAR ADC are enhanced in two directions. To reduce the power dissipation, a power saving strategy has been proposed. Also, several foreground calibration methods for SAR ADCs have been proposed to reduce power dissipation and enhance conversion accuracy. The design was fabricated in 40nm CMOS technology. Measurement results after calibration showed a SFDR of 82.2 dB, and a THD improvement of 22.5 dB. Finally, two new schemes to realize teraohm on-chip resistance are presented. One of the schemes utilizes a switched-capacitor array, and the other utilizes a switch-capacitor ladder. Using these schemes, large resistances can be fabricated with standard CMOS process in an affordable chip area.
Book Synopsis Design Techniques for Low Power High Speed Successive Approximation Analog-to-digital Converters by : Jiaming Lin
Download or read book Design Techniques for Low Power High Speed Successive Approximation Analog-to-digital Converters written by Jiaming Lin and published by . This book was released on 2013 with total page 75 pages. Available in PDF, EPUB and Kindle. Book excerpt: This dissertation presents two high-speed pipeline successive approximation analog-to-digital converters (SAR ADCs). Capacitive DACs and resistive DACs are utilized in these two pipeline SAR ADCs, respectively. The pipeline SAR ADC with capacitive DACs can save 50% switching power compared with other time-interleaved SAR ADCs since the total capacitance of the DACs in this ADC is more than 50% less than the conventional time-interleave ones. Several switching techniques are implemented to alleviate the impact from the parasitic capacitance and improve the performance. The pipeline SAR ADC with resistive DACs overcomes the influence from the parasitic capacitance with negligible static power consumption on the resistive DACs. Also, the complicated switching techniques can be avoided to simplify the timing logic. To verify the above two architectures, two chips were designed and fabricated in 40nm CMOS process. Finally, a new architecture of multi-step capacitive-splitting SAR ADC is proposed for low power applications. By using two identical capacitor-splitting capacitor arrays, the switching power and capacitor area can be reduced significantly.
Book Synopsis Time-interleaved Analog-to-Digital Converters by : Simon Louwsma
Download or read book Time-interleaved Analog-to-Digital Converters written by Simon Louwsma and published by Springer Science & Business Media. This book was released on 2010-09-08 with total page 148 pages. Available in PDF, EPUB and Kindle. Book excerpt: Time-interleaved Analog-to-Digital Converters describes the research performed on low-power time-interleaved ADCs. A detailed theoretical analysis is made of the time-interleaved Track & Hold, since it must be capable of handling signals in the GHz range with little distortion, and minimal power consumption. Timing calibration is not attractive, therefore design techniques are presented which do not require timing calibration. The design of power efficient sub-ADCs is addressed with a theoretical analysis of a successive approximation converter and a pipeline converter. It turns out that the first can consume about 10 times less power than the latter, and this conclusion is supported by literature. Time-interleaved Analog-to-Digital Converters describes the design of a high performance time-interleaved ADC, with much attention for practical design aspects, aiming at both industry and research. Measurements show best-inclass performance with a sample-rate of 1.8 GS/s, 7.9 ENOBs and a power efficiency of 1 pJ/conversion-step.
Book Synopsis Circuit Design for Realization of a 16 Bit 1MS/s Successive Approximation Register Analog-to-Digital Converter by : Cody R. Brenneman
Download or read book Circuit Design for Realization of a 16 Bit 1MS/s Successive Approximation Register Analog-to-Digital Converter written by Cody R. Brenneman and published by . This book was released on 2010 with total page 242 pages. Available in PDF, EPUB and Kindle. Book excerpt: Abstract: As the use of digital systems continues to grow, there is an increasing need to convert analog information into the digital domain. Successive Approximation Register (SAR) analog-to-digital converters are used extensively in this regard due to their high resolution, small die area, and moderate conversion speeds. However, capacitor mismatch within the SAR converter is a limiting factor in its accuracy and resolution. Without some form of calibration, a SAR converter can only reasonably achieve an accuracy of 10 bits. The Split-ADC technique is a digital, deterministic, background self-calibration algorithm that can be applied to the SAR converter. This thesis describes the circuit design and physical implementation of a novel 16-bit 1MS/s SAR analog-to-digital converter for use with the Split-ADC calibration algorithm. The system was designed using the Jazz 0.18um CMOS process, successfully operates at 1MS/s, and consumes a die area of 1.2mm2. The calibration algorithm was applied, showing an improvement in the overall accuracy of the converter.
Book Synopsis Principles of Data Conversion System Design by : Behzad Razavi
Download or read book Principles of Data Conversion System Design written by Behzad Razavi and published by Wiley-IEEE Press. This book was released on 1995 with total page 280 pages. Available in PDF, EPUB and Kindle. Book excerpt: This advanced text and reference covers the design and implementation of integrated circuits for analog-to-digital and digital-to-analog conversion. It begins with basic concepts and systematically leads the reader to advanced topics, describing design issues and techniques at both circuit and system level. Gain a system-level perspective of data conversion units and their trade-offs with this state-of-the art book. Topics covered include: sampling circuits and architectures, D/A and A/D architectures; comparator and op amp design; calibration techniques; testing and characterization; and more!
Book Synopsis An Implementation of 1.5 Bits/Stage Low Power Successive Approximation Register Analog to Digital Converter by Using on Chip Calibration by :
Download or read book An Implementation of 1.5 Bits/Stage Low Power Successive Approximation Register Analog to Digital Converter by Using on Chip Calibration written by and published by . This book was released on 2015 with total page 89 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis Design Techniques for Low Power ADCs by : Wenhuan Yu
Download or read book Design Techniques for Low Power ADCs written by Wenhuan Yu and published by . This book was released on 2010 with total page 152 pages. Available in PDF, EPUB and Kindle. Book excerpt: This dissertation presents an incremental analog-to-digital converter (ADC) with digital digital-to-analog converter (DAC) mismatch correction. A theoretical time-domain analysis technique was developed to predict the noise performance of the incremental ADC, and a new optimization technique was proposed to minimize the output noise. In the calibration mode, the incremental ADC itself is used to measure the mismatches of the internal multi-bit DAC. Three new calibration techniques, equation-solving calibration, inter-DAC mismatch calibration and modified "Sarhang-Nejad" calibration are proposed. To verify the above techniques, a test chip was designed and fabricated in 0.18 [mu]m CMOS process. The chip can work in single-sampling or double-sampling mode. Chopping with a fractal sequence is used to eliminate 1/f noise. The calibration circuit was implemented to calibrate the multi-bit DAC mismatches the in single-sampling mode and inter-DAC mismatches in the double-sampling mode. Finally, two new design techniques for low-power ADCs, the two-step split-junction successive-approximation register (SAR) ADC and the hybrid cascaded [Delta Sigma] ADC, are proposed.
Book Synopsis Design Techniques for Successive Approximation Register Analog-to-digital Converters by : Tao Tong
Download or read book Design Techniques for Successive Approximation Register Analog-to-digital Converters written by Tao Tong and published by . This book was released on 2011 with total page 42 pages. Available in PDF, EPUB and Kindle. Book excerpt: Successive approximation register analog-to-digital converters (SAR ADCs) have been widely used for medium-speed, medium-resolution applications due to their excellent power efficiency and digital compatibility. Recently, SAR ADCs are also penetrating into the applications which have been earlier dominated by delta-sigma ADCs and pipeline ADCs. However, the resolution of SAR ADCs is limited by component mismatch, and their speed is generally slow due to serial operation. In this work, several system innovations and design techniques are investigated for SAR ADCs. First, a semi-synchronous clocking is proposed to optimize the comparator resolving time and DAC settling time in the SAR conversion. Simulations show a 40% speed-up compared with conventional synchronous processing. A self-calibration technique to correct the capacitor mismatch error is also introduced. The proposed calibration algorithm is verified to be insensitive to the non-idealities in the calibration DACs.
Book Synopsis Charge-Sharing SAR ADCs for Low-Voltage Low-Power Applications by : Taimur Rabuske
Download or read book Charge-Sharing SAR ADCs for Low-Voltage Low-Power Applications written by Taimur Rabuske and published by Springer. This book was released on 2018-06-12 with total page 165 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book introduces readers to the potential of charge-sharing (CS) successive approximation register (SAR) analog-to-digital converters (ADCs), while providing extensive analysis of the factors that limit the performance of the CS topology. The authors present guidelines and useful techniques for mitigating the limitations of the architecture, while focusing on the implementation under restricted power budgets and voltage supplies.
Book Synopsis Low Power High Performance Successive Approximation Analog to Digital Converter by : Rabeeh Majidi
Download or read book Low Power High Performance Successive Approximation Analog to Digital Converter written by Rabeeh Majidi and published by . This book was released on 2010 with total page 112 pages. Available in PDF, EPUB and Kindle. Book excerpt:
