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All Digital Background Calibration For Time Interleaved And Successive Approximation Register Analog To Digital Converters
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Book Synopsis All Digital, Background Calibration for Time-Interleaved and Successive Approximation Register Analog-to-Digital Converters by : Christopher Leonidas David
Download or read book All Digital, Background Calibration for Time-Interleaved and Successive Approximation Register Analog-to-Digital Converters written by Christopher Leonidas David and published by . This book was released on 2010 with total page 370 pages. Available in PDF, EPUB and Kindle. Book excerpt: Abstract: The growth of digital systems underscores the need to convert analog information to the digital domain at high speeds and with great accuracy. Analog-to-Digital Converter (ADC) calibration is often a limiting factor, requiring longer calibration times to achieve higher accuracy. The goal of this dissertation is to perform a fully digital background calibration using an arbitrary input signal for A/D converters. The work presented here adapts the cyclic "Split-ADC" calibration method to the time interleaved (TI) and successive approximation register (SAR) architectures. The TI architecture has three types of linear mismatch errors: offset, gain and aperture time delay. By correcting all three mismatch errors in the digital domain, each converter is capable of operating at the fastest speed allowed by the process technology. The total number of correction parameters required for calibration is dependent on the interleaving ratio, M. To adapt the "Split-ADC" method to a TI system, 2M+1 half-sized converters are required to estimate 3(2M+1) correction parameters. This thesis presents a 4:1 "Split-TI" converter that achieves full convergence in less than 400,000 samples. The SAR architecture employs a binary weight capacitor array to convert analog inputs into digital output codes. Mismatch in the capacitor weights results in non-linear distortion error. By adding redundant bits and dividing the array into individual unit capacitors, the "Split-SAR" method can estimate the mismatch and correct the digital output code. The results from this work show a reduction in the non-linear distortion with the ability to converge in less than 750,000 samples.
Book Synopsis An Equalization-based Adaptive Digital Background Calibration Technique for Successive Approximation Analog-to-digital Converter and Time-interleaved Converter Array by : Wenbo Liu
Download or read book An Equalization-based Adaptive Digital Background Calibration Technique for Successive Approximation Analog-to-digital Converter and Time-interleaved Converter Array written by Wenbo Liu and published by . This book was released on 2008 with total page 78 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis Digital Background Calibration of Analog-to-digital Converters Using a Calibration Queue by : Ozan Ersan Erdoğan
Download or read book Digital Background Calibration of Analog-to-digital Converters Using a Calibration Queue written by Ozan Ersan Erdoğan and published by . This book was released on 1999 with total page 250 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis Calibration Techniques for Time-Interleaved SAR A/D Converters by : Dusan Vlastimir Stepanovic
Download or read book Calibration Techniques for Time-Interleaved SAR A/D Converters written by Dusan Vlastimir Stepanovic and published by . This book was released on 2012 with total page 228 pages. Available in PDF, EPUB and Kindle. Book excerpt: Benefits of technology scaling and the flexibility of digital circuits favor the digital signal processing in many applications, placing additional burden to the analog-to-digital con- verters (ADCs). This has created a need for energy-efficient ADCs in the GHz sampling frequency and moderate effective resolution range. A dominantly digital nature of successive approximation register (SAR) ADCs makes them a good candidate for an energy-efficient and scalable design, but its sequential operation limits its applicability in the GHz sampling range. Time-interleaving can be used to extend the efficiency of the SAR ADCs to the higher frequencies if the mismatches between the interleaved ADC channels can be handled in an efficient manner. New calibration techniques are proposed for time-interleaved SAR ADCs capable of cor- recting the gain, offset and timing mismatches, as well as the static nonlinearities of individ- ual ADC channels stemming from the capacitor mismatches. The techniques are based on introducing two additional calibration channels that are identical to all other time-interleaved channels and the use of the least mean square algorithm (LMS). The calibration of the chan- nel offset and gain mismatches, as well as the capacitor mismatches, is performed in the background using digital post-processing. The timing mismatches between channels are cor- rected using a mixed-signal feedback, where all calculations are performed in the digital do- main, but the actual timing correction is done in the analog domain by fine-tuning the edges of the sampling clocks. These calibration techniques enable a design of time-interleaved con- verters that use minimum-sized capacitors and operate in the thermal-noise-limited regime for maximum energy and area efficiency. The techniques are demonstrated on a time-interleaved converter that interleaves 24 channels designed in a 65nm CMOS technology. The ADC uses the smallest capacitor value of only 50aF, achieves 50.9dB SNDR at fs = 2.8GHz with the effective-resolution bandwidth higher than the Nyquist frequency, while consuming only 44.6 mW of power.
Book Synopsis All Digital Calibration for High-resolution Successive-approximation Register Analog-to-digital Converter by : 廖亦勛
Download or read book All Digital Calibration for High-resolution Successive-approximation Register Analog-to-digital Converter written by 廖亦勛 and published by . This book was released on 2022 with total page 0 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis Background Calibration of Timing Skew in Time-interleaved A/D Converters by : Manar Ibrahim El-Chammas
Download or read book Background Calibration of Timing Skew in Time-interleaved A/D Converters written by Manar Ibrahim El-Chammas and published by Stanford University. This book was released on 2010 with total page 155 pages. Available in PDF, EPUB and Kindle. Book excerpt: The increasing data rate of wireline communication systems leads to more inter-symbol interference, due to the dispersive properties of the communication channel. This requires more complex equalization blocks to meet the required bit-error rate. One solution is to use an Analog-to-Digital Converter (ADC) in the front-end, thus enabling a digitally-equalized serial link. To achieve the high-data rates of these communication systems, a time-interleaved ADC is typically used. However, this type of ADC suffers from several time-varying errors, the most prominent of which is timing skew. This thesis introduces a statistics-based background calibration algorithm that compensates for the effect of timing skew. To demonstrate the background calibration algorithm, a proof-of-concept 5 bit 12 GS/s flash ADC has been fabricated in a 65 nm CMOS process. The design of this ADC takes into consideration the tight power bounds imposed on serial links by optimizing both the time-interleaved and the sub-ADC architecture. Power consumption is further reduced by using calibration circuits to correct the offset of the flash ADC's comparators. In the measured results, the timing skew correction improves the dynamic performance of the time-interleaved ADC by 12 dB, and the proof-of-concept ADC has the lowest published power consumption for ADCs with sample rates higher than 10 GS/s.
Book Synopsis Time-interleaved SAR ADC with Signal Independent Background Timing Calibration by : Christopher Kaiti Su
Download or read book Time-interleaved SAR ADC with Signal Independent Background Timing Calibration written by Christopher Kaiti Su and published by . This book was released on 2020 with total page 0 pages. Available in PDF, EPUB and Kindle. Book excerpt: This thesis describes a background-calibration technique that overcomes timing errors in time-interleaved analog-to-digital converters (ADCs) in a way that is almost independent of the user-provided ADC input signal. Additive dither is widely used to achieve signal-independent background calibration of many errors in data converters [1]. For example, this technique has been used to calibrate for gain mismatch in time-interleaved ADCs [2]. In most cases, however, binary dither has been used, and binary dither is not able to detect timing errors when the user-provided ADC input is zero or constant because timing errors do not produce amplitude errors when the ADC input is constant. This thesis presents a study of the use of a random ramp-based dither signal to calibrate for timing errors in time-interleaved ADCs. To demonstrate the dither-based timing calibration, a prototype 10-bit 500-MS/s 4-channel ADC was fabricated in 40-nm CMOS. With the proposed timing calibration, the Signal-to-Noise-and-Distortion Ratio (SNDR) is 50.1 dB with a user-provided input at 249 MHz while consuming 6.2 mW, giving a figure of merit (FoM) of 48.4 fJ/step. Disabling the ramp after the timing calibration converges improves the SNDR to 51 dB and reduces the power dissipation to 5.8 mW as well as the FoM to 39.8 fJ/step. [1] H. E. Hilton, "A 10-MHz Analog-to-Digital Converter with 110-dB Linearity," Hewlett-Packard Journal, vol. 44, No. 5, pp. 105-112, Oct. 1993. [2] D. Fu, K. C. Dyer, P. J. Hurst, and S. H. Lewis, "A Digital Background Calibration Technique for Time-Interleaved Analog-to-Digital Converters," IEEE J. of Solid-State Circuits, vol. 33, No. 12, pp.1904-1911, Dec. 1998.
Book Synopsis A Full Range Digital Calibration in 12-bit Successive Approximation Register Analog-to-Digital Converter by : 林葦婷
Download or read book A Full Range Digital Calibration in 12-bit Successive Approximation Register Analog-to-Digital Converter written by 林葦婷 and published by . This book was released on 2013 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis Background Digital Calibration of SAR ADC with Fast FPGA Emulation by : Guanhua Wang
Download or read book Background Digital Calibration of SAR ADC with Fast FPGA Emulation written by Guanhua Wang and published by . This book was released on 2013 with total page 100 pages. Available in PDF, EPUB and Kindle. Book excerpt: This dissertation presents a background calibration technique of successive approximation register (SAR) analog-to-digital converter (ADC) and a FPGA emulation platform for fast verification. The bit-weight calibration of a sub-binary weighted SAR ADC is based on the internal redundancy dithering (IRD) technique. A coarse ADC is employed as the reference path to remove the input interference problem in correlation-based background calibration. A custom FPGA emulation platform is developed to verify the proposed calibration approach, which achieves a 3000 speedup for the same simulation executed on a general-purpose microprocessor. Emulation results show that the signal-to-noise plus distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are improved from 56dB to 89dB and 64dB to 115dB, respectively, for a sub-binary-weighted 16-bit SAR ADC with 1% DAC mismatch errors.
Book Synopsis Applying the "split-ADC" Architecture to a 16 Bit, 1 MS/s Differential Successive Approximation Analog-to-digital Converter by :
Download or read book Applying the "split-ADC" Architecture to a 16 Bit, 1 MS/s Differential Successive Approximation Analog-to-digital Converter written by and published by . This book was released on 2008 with total page 350 pages. Available in PDF, EPUB and Kindle. Book excerpt: Abstract: Successive Approximation (SAR) analog-to-digital converters are used extensively in biomedical applications such as CAT scan due to the high resolution they offer. Capacitor mismatch in the SAR converter is a limiting factor for its accuracy and resolution. Without some form of calibration, a SAR converter can only achieve 10 bit accuracy. In industry, the CAL-DAC approach is a popular approach for calibrating the SAR ADC, but this approach requires significant test time. This thesis applies the "Split-ADC" architecture with a deterministic, digital, and background self-calibration algorithm to the SAR converter to minimize test time. In this approach, a single ADC is split into two independent halves. The two split ADCs convert the same input sample and produce two output codes. The ADC output is the average of these two output codes. The difference between these two codes is used as a calibration signal to estimate the errors of the calibration parameters in a modified Jacobi method. The estimates are used to update calibration parameters are updated in a negative feedback LMS procedure. The ADC is fully calibrated when the difference signal goes to zero on average. This thesis focuses on the specific implementation of the "Split-ADC" self-calibrating algorithm on a 16 bit, 1 MS/s differential SAR ADC. The ADC can be calibrated with 105 conversions. This represents an improvement of 3 orders of magnitude over existing statistically-based calibration algorithms. Simulation results show that the linearity of the calibrated ADC improves to within "1 LSB.
Book Synopsis Digital Background Calibration of a 10-b 40-MS/s Parallel Pipelined ADC by : Daihong Fu
Download or read book Digital Background Calibration of a 10-b 40-MS/s Parallel Pipelined ADC written by Daihong Fu and published by . This book was released on 1998 with total page 254 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis Digital Background Calibration for Pipelined and Time-interleaved Analog-to-digital Converters by : Kamal Elsankary
Download or read book Digital Background Calibration for Pipelined and Time-interleaved Analog-to-digital Converters written by Kamal Elsankary and published by . This book was released on 2006 with total page 274 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis A Fast-Fourier-Transform-Based Digital Calibration Technique for Successive-Approximation-Register Analog-to-Digital Converters by : 李育丞
Download or read book A Fast-Fourier-Transform-Based Digital Calibration Technique for Successive-Approximation-Register Analog-to-Digital Converters written by 李育丞 and published by . This book was released on 2018 with total page 81 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis CMOS Data Converters for Communications by : Mikael Gustavsson
Download or read book CMOS Data Converters for Communications written by Mikael Gustavsson and published by Springer Science & Business Media. This book was released on 2005-12-15 with total page 394 pages. Available in PDF, EPUB and Kindle. Book excerpt: CMOS Data Converters for Communications distinguishes itself from other data converter books by emphasizing system-related aspects of the design and frequency-domain measures. It explains in detail how to derive data converter requirements for a given communication system (baseband, passband, and multi-carrier systems). The authors also review CMOS data converter architectures and discuss their suitability for communications. The rest of the book is dedicated to high-performance CMOS data converter architecture and circuit design. Pipelined ADCs, parallel ADCs with an improved passive sampling technique, and oversampling ADCs are the focus for ADC architectures, while current-steering DAC modeling and implementation are the focus for DAC architectures. The principles of the switched-current and the switched-capacitor techniques are reviewed and their applications to crucial functional blocks such as multiplying DACs and integrators are detailed. The book outlines the design of the basic building blocks such as operational amplifiers, comparators, and reference generators with emphasis on the practical aspects. To operate analog circuits at a reduced supply voltage, special circuit techniques are needed. Low-voltage techniques are also discussed in this book. CMOS Data Converters for Communications can be used as a reference book by analog circuit designers to understand the data converter requirements for communication applications. It can also be used by telecommunication system designers to understand the difficulties of certain performance requirements on data converters. It is also an excellent resource to prepare analog students for the new challenges ahead.
Book Synopsis Blind Calibration for Time-interleaved Analog-to-digital Converters by : Yuhui Huang
Download or read book Blind Calibration for Time-interleaved Analog-to-digital Converters written by Yuhui Huang and published by . This book was released on 2006 with total page 326 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis Signal Processing and Analysis of Electrical Circuit by : Adam Glowacz
Download or read book Signal Processing and Analysis of Electrical Circuit written by Adam Glowacz and published by MDPI. This book was released on 2020-03-13 with total page 604 pages. Available in PDF, EPUB and Kindle. Book excerpt: This Special Issue with 35 published articles shows the significance of the topic “Signal Processing and Analysis of Electrical Circuit”. This topic has been gaining increasing attention in recent times. The presented articles can be categorized into four different areas: signal processing and analysis methods of electrical circuits; electrical measurement technology; applications of signal processing of electrical equipment; fault diagnosis of electrical circuits. It is a fact that the development of electrical systems, signal processing methods, and circuits has been accelerating. Electronics applications related to electrical circuits and signal processing methods have gained noticeable attention in recent times. The methods of signal processing and electrical circuits are widely used by engineers and scientists all over the world. The constituent papers represent a significant contribution to electronics and present applications that can be used in industry. Further improvements to the presented approaches are required for realizing their full potential.
Book Synopsis Statistical Calibration for Two-step Analog-to-digital Conversion by : Yi-Long Yu
Download or read book Statistical Calibration for Two-step Analog-to-digital Conversion written by Yi-Long Yu and published by . This book was released on 2019 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: This thesis describes a two-step, hybrid and reconfigurable data converter using statistical calibration. The two-step analog-to-digital converter (ADC) has a front-end successive-approximation register (SAR) ADC and a back-end time-domain (TD) ADC, which together form a hybrid converter. An inter-stage sample-and-hold amplifier (SHA) doubles the operating speed by allowing the operation to be pipelined. A reconfigurable characteristic allows the converter resolution to be adjusted to be 8, 10 or 12 bits. Digital statistical calibration of ADCs can be implemented without any changes to the analog circuits, which allows it to be compatible with the characteristics of scaled CMOS, allowing potential savings in area and power dissipation. Unfortunately, statistical calibration requires some assumptions about the input density. However, these assumptions are less restrictive in this work than in previous work for two reasons. First, statistical calibration of the mismatch in the front-end capacitor arrays requires only that the input distribution be smooth (instead of requiring that the input be known as in previous work). Also, statistical calibration of inter-stage and back-end errors relies on the assumption that the residue or quantization error from the first stage is uniformly distributed. This residue characteristic holds for many ADC inputs and is intuitively explained in this thesis. To demonstrate the statistical calibration, a prototype ADC is fabricated in 40-nm CMOS technology. In the 12-bit mode at 20 MS/s, the maximum SNDR is 59 dB before calibration and 68 dB after calibration, using 6.2 fJ per conversion-step, excluding the power dissipation required by the calibration and 9.1 fJ per conversion-step including the estimated power dissipation for the calibration.
