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A Robust Low Power Static Random Access Memory Cell Design
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Book Synopsis Low Power and Reliable SRAM Memory Cell and Array Design by : Koichiro Ishibashi
Download or read book Low Power and Reliable SRAM Memory Cell and Array Design written by Koichiro Ishibashi and published by Springer Science & Business Media. This book was released on 2011-08-18 with total page 154 pages. Available in PDF, EPUB and Kindle. Book excerpt: Success in the development of recent advanced semiconductor device technologies is due to the success of SRAM memory cells. This book addresses various issues for designing SRAM memory cells for advanced CMOS technology. To study LSI design, SRAM cell design is the best materials subject because issues about variability, leakage and reliability have to be taken into account for the design.
Book Synopsis A Robust Low Power Static Random Access Memory Cell Design by : A. V. Rama Raju Pusapati
Download or read book A Robust Low Power Static Random Access Memory Cell Design written by A. V. Rama Raju Pusapati and published by . This book was released on 2018 with total page 83 pages. Available in PDF, EPUB and Kindle. Book excerpt: Stability of a Static Random Access Memory (SRAM) cell is an important factor when considering an SRAM cell for any application. The Static Noise Margin (SNM) of a cell, which determines the stability, varies under different operating conditions. Based on the performance of three existing SRAM cell designs, 6T, 8T and 10T, a 10 Transistor SRAM cell is proposed which has good stability and has the advantage of reduced read power when compared to 6T and 8T SRAM cells. The proposed 10T SRAM cell has a single-ended read circuit which improves SNM over the 6T cell. The proposed 10T cell doesn't require a pre-charge circuit and this in-turn improves read power and also reduces the read time since there is no need to pre-charge the bit-line before reading it. The Read SNM and Hold SNM of the proposed cell at a VDD of 1V and at 25°C is 254mV. The measured RSNM, HSNM and Write SNM at temperatures 0°C, 40°C, 80°C and 120°C and also at supply voltages 1V, 0.8V and 0.6V show the design is robust. The Write SNM of the proposed cell at a VDD of 1V and Pull-up Ratio of 1 is 275mV. Finally, a 32-byte memory array is built using the proposed 10T SRAM cell and the read, write times are 149ps and 21.6ps, respectively. The average power consumed by the 32-byte array over a 12ns period is 13.8uW. All the designs are done in the 32nm FinFET technology.
Book Synopsis Robust SRAM Designs and Analysis by : Jawar Singh
Download or read book Robust SRAM Designs and Analysis written by Jawar Singh and published by Springer Science & Business Media. This book was released on 2012-08-01 with total page 176 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book provides a guide to Static Random Access Memory (SRAM) bitcell design and analysis to meet the nano-regime challenges for CMOS devices and emerging devices, such as Tunnel FETs. Since process variability is an ongoing challenge in large memory arrays, this book highlights the most popular SRAM bitcell topologies (benchmark circuits) that mitigate variability, along with exhaustive analysis. Experimental simulation setups are also included, which cover nano-regime challenges such as process variation, leakage and NBTI for SRAM design and analysis. Emphasis is placed throughout the book on the various trade-offs for achieving a best SRAM bitcell design. Provides a complete and concise introduction to SRAM bitcell design and analysis; Offers techniques to face nano-regime challenges such as process variation, leakage and NBTI for SRAM design and analysis; Includes simulation set-ups for extracting different design metrics for CMOS technology and emerging devices; Emphasizes different trade-offs for achieving the best possible SRAM bitcell design.
Book Synopsis Energy Efficient and Reliable Embedded Nanoscale SRAM Design by : Bhupendra Singh Reniwal
Download or read book Energy Efficient and Reliable Embedded Nanoscale SRAM Design written by Bhupendra Singh Reniwal and published by CRC Press. This book was released on 2023-11-29 with total page 221 pages. Available in PDF, EPUB and Kindle. Book excerpt: This reference text covers a wide spectrum for designing robust embedded memory and peripheral circuitry. It will serve as a useful text for senior undergraduate and graduate students and professionals in areas including electronics and communications engineering, electrical engineering, mechanical engineering, and aerospace engineering. Discusses low-power design methodologies for static random-access memory (SRAM) Covers radiation-hardened SRAM design for aerospace applications Focuses on various reliability issues that are faced by submicron technologies Exhibits more stable memory topologies Nanoscale technologies unveiled significant challenges to the design of energy- efficient and reliable SRAMs. This reference text investigates the impact of process variation, leakage, aging, soft errors and related reliability issues in embedded memory and periphery circuitry. The text adopts a unique way to explain the SRAM bitcell, array design, and analysis of its design parameters to meet the sub-nano-regime challenges for complementary metal-oxide semiconductor devices. It comprehensively covers low- power-design methodologies for SRAM, exhibits more stable memory topologies, and radiation-hardened SRAM design for aerospace applications. Every chapter includes a glossary, highlights, a question bank, and problems. The text will serve as a useful text for senior undergraduate students, graduate students, and professionals in areas including electronics and communications engineering, electrical engineering, mechanical engineering, and aerospace engineering. Discussing comprehensive studies of variability-induced failure mechanism in sense amplifiers and power, delay, and read yield trade-offs, this reference text will serve as a useful text for senior undergraduate, graduate students, and professionals in areas including electronics and communications engineering, electrical engineering, mechanical engineering, and aerospace engineering. It covers the development of robust SRAMs, well suited for low-power multi-core processors for wireless sensors node, battery-operated portable devices, personal health care assistants, and smart Internet of Things applications.
Book Synopsis Novel High Performance Ultra Low Power Static Random Access Memories (SRAMs) Based on Next Generation Technologies by : Mahmood Uddin Mohammed
Download or read book Novel High Performance Ultra Low Power Static Random Access Memories (SRAMs) Based on Next Generation Technologies written by Mahmood Uddin Mohammed and published by . This book was released on 2019 with total page 121 pages. Available in PDF, EPUB and Kindle. Book excerpt: Next Big Thing Is Surely Small: Nanotechnology Can Bring Revolution. Nanotechnology leads the world towards many new applications in various fields of computing, communication, defense, entertainment, medical, renewable energy and environment. These nanotechnology applications require an energy-efficient memory system to compute and process. Among all the memories, Static Random Access Memories (SRAMs) are high performance memories and occupies more than 50% of any design area. Therefore, it is critical to design high performance and energy-efficient SRAM design. Ultra low power and high speed applications require a new generation memory capable of operating at low power as well as low execution time. In this thesis, a novel 8T SRAM design is proposed that offers significantly faster access time and lowers energy consumption along with better read stability and write ability. The proposed design can be used in the conventional SRAM as well as in computationally intensive applications like neural networks and machine learning classifiers [1]-[4]. Novel 8T SRAM design offers higher energy efficiency, reliability, robustness and performance compared to the standard 6T and other existing 8T and 9T designs. It offers the advantages of a 10T SRAM without the additional area, delay and power overheads of the 10T SRAM. The proposed 8T SRAM would be able to overcome many other limitations of the conventional 6T and other 7T, 8T and 9T designs. The design employs single bitline for the write operation, therefore the number of write drivers are reduced. The defining feature of the proposed 8T SRAM is its hybrid design, which is the combination of two techniques: (i) the utilization of single-ended bitline and (ii) the utilization of virtual ground. The single-ended bitline technique ensures separate read and write operations, which eventually reduces the delay and power consumption during the read and write operations. It's independent read and write paths allow the use of the minimum sized access transistors and aid in a disturb-free read operation. The virtual ground weakens the positive feedback in the SRAM cell and improves its write ability. The virtual ground technique is also used to reduce leakages. The proposed design does not require precharging the bitlines for the read operation, which reduces the area and power overheads of the memory system by eliminating the precharging circuit. The design isolates the storage node from the read path, which improves the read stability. For reliability study, we have investigated the static noise margin (SNM) of the proposed 8T SRAM, for which, we have used two methods – (i) the traditional SNM method with the butterfly curve, (ii) the N-curve method A comparative analysis is performed between the proposed and the existing SRAM designs in terms of area, total power consumption during the read and write operations, and stability and reliability. All these advantages make the proposed 8T SRAM design an ideal candidate for the conventional and computationally intensive applications like machine learning classifier and deep learning neural network. In addition to this, there is need for next generation technologies to design SRAM memory because the conventional CMOS technology is approaching its physical and performance boundaries and as a consequence, becoming incompatible with ultra-low-power applications. Emerging devices such as Tunnel Field Effect Transistor (TFET)) and Graphene Nanoribbon Field Effect Transistor (GNRFET) devices are highly potential candidates to overcome the limitations of MOSFET because of their ability to achieve subthreshold slopes below 60 mV/decade and very low leakage currents [6]-[9]. This research also explores novel TFET and GNRFET based 6T SRAM. The thesis evaluates the standby leakage power in the Tunnel FET (TFET) based 6T SRAM cell for different pull-up, pull-down, and pass-gate transistors ratios (PU: PD: PG) and compared to 10nm FinFET based 6T SRAM designs. It is observed that the 10nm TFET based SRAMs have 107.57%, 163.64%, and 140.44% less standby leakage power compared to the 10nm FinFET based SRAMs when the PU: PD: PG ratios are 1:1:1, 1:5:2 and 2:5:2, respectively. The thesis also presents an analysis of the stability and reliability of sub-10nm TFET based 6T SRAM circuit with a reduced supply voltage of 500mV. The static noise margin (SNM), which is a critical measure of SRAM stability and reliability, is determined for hold, read and write operations of the 6T TFET SRAM cell. The robustness of the optimized TFET based 6T SRAM circuit is also evaluated at different supply voltages. Simulations were done in HSPICE and Cadence tools. From the analysis, it is clear that the main advantage of the TFET based SRAM would be the significant improvement in terms of leakage or standby power consumption. Compared to the FinFET based SRAM the standby leakage power of the T-SRAMs are 107.57%, 163.64%, and 140.44% less for 1:1:1, 1:5:2 and 2:5:2 configurations, respectively. Since leakage/standby power is the primary source of power consumption in the SRAM, and the overall system energy efficiency depends on SRAM power consumption, TFET based SRAM would lead to massive improvement of the energy efficiency of the system. Therefore, T-SRAMs are more suitable for ultra-low power applications. In addition to this, the thesis evaluates the standby leakage power of types of Graphene Nanoribbon FETs based 6T SRAM bitcell and compared to 10nm FinFET based 6T SRAM bitcell. It is observed that the 10nm MOS type GNRFET based SRAMs have 16.43 times less standby leakage power compared to the 10nm FinFET based SRAMs. The double gate SB-GNRFET based SRAM consumes 1.35E+03 times less energy compared to the 10nm FinFET based SRAM during write. However, during read double gate SB-GNRFET based SRAM consume 15 times more energy than FinFET based SRAM. It is also observed that GNRFET based SRAMs are more stable and reliable than FinFET based SRAM.
Book Synopsis Low Power Designs in Nanodevices and Circuits for Emerging Applications by : Shilpi Birla
Download or read book Low Power Designs in Nanodevices and Circuits for Emerging Applications written by Shilpi Birla and published by CRC Press. This book was released on 2023-11-14 with total page 339 pages. Available in PDF, EPUB and Kindle. Book excerpt: This reference textbook discusses low power designs for emerging applications. This book focuses on the research challenges associated with theory, design, and applications towards emerging Microelectronics and VLSI device design and developments, about low power consumptions. The advancements in large-scale integration technologies are principally responsible for the growth of the electronics industry. This book is focused on senior undergraduates, graduate students, and professionals in the field of electrical and electronics engineering, nanotechnology. This book: Discusses various low power techniques and applications for designing efficient circuits Covers advance nanodevices such as FinFETs, TFETs, CNTFETs Covers various emerging areas like Quantum-Dot Cellular Automata Circuits and FPGAs and sensors Discusses applications like memory design for low power applications using nanodevices The number of options for ICs in control applications, telecommunications, high-performance computing, and consumer electronics continues to grow with the emergence of VLSI designs. Nanodevices have revolutionized the electronics market and human life; it has impacted individual life to make it more convenient. They are ruling every sector such as electronics, energy, biomedicine, food, environment, and communication. This book discusses various emerging low power applications using CMOS and other emerging nanodevices.
Book Synopsis Design and Implementation of High Speed, Low Power Static Random Access Memory (SRAM) by : David Hentrich
Download or read book Design and Implementation of High Speed, Low Power Static Random Access Memory (SRAM) written by David Hentrich and published by . This book was released on 2007 with total page 286 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis VLSI Design and Test by : S. Rajaram
Download or read book VLSI Design and Test written by S. Rajaram and published by Springer. This book was released on 2019-01-24 with total page 722 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book constitutes the refereed proceedings of the 22st International Symposium on VLSI Design and Test, VDAT 2018, held in Madurai, India, in June 2018. The 39 full papers and 11 short papers presented together with 8 poster papers were carefully reviewed and selected from 231 submissions. The papers are organized in topical sections named: digital design; analog and mixed signal design; hardware security; micro bio-fluidics; VLSI testing; analog circuits and devices; network-on-chip; memory; quantum computing and NoC; sensors and interfaces.
Book Synopsis Stability and Static Noise Margin Analysis of Static Random Access Memory by : Rajasekhar Keerthi
Download or read book Stability and Static Noise Margin Analysis of Static Random Access Memory written by Rajasekhar Keerthi and published by . This book was released on 2007 with total page 63 pages. Available in PDF, EPUB and Kindle. Book excerpt: The transistor mismatch can be described as two closely placed identical transistors have important differences in their electrical parameters as threshold voltage, body factor and current factor and make integrated circuit design and fabrication less predictable and controllable. Stability of a static random access memory (SRAM) is defined through its ability to retain the data at low-VDD. It is seriously affected by increased variability of transistor mismatch and decreased supply voltage and therefore becomes a major limitation of overall performance of low-voltage SRAM in nanometer CMOS process. The stability limitation is addressed through the design of a seven-transistor (7T) SRAM cell and of which the stability analysis and comparison with the conventional 6T SRAM cell is presented. This research also presents two 8-bit SRAM designs implemented by 6T and 7T SRAM cells respectively. The robustness of both designs is tested and verified through transistor mismatch and environmental process variations. Results obtained show 7T SRAM outperform 6T SRAM when stability is of a major concern.
Book Synopsis Nanoelectronics for Next-Generation Integrated Circuits by : Rohit Dhiman
Download or read book Nanoelectronics for Next-Generation Integrated Circuits written by Rohit Dhiman and published by CRC Press. This book was released on 2022-11-23 with total page 255 pages. Available in PDF, EPUB and Kindle. Book excerpt: The incessant scaling of complementary metal-oxide semiconductor (CMOS) technology has resulted in significant performance improvements in very-large-scale integration (VLSI) design techniques and system architectures. This trend is expected to continue in the future, but this requires breakthroughs in the design of nano-CMOS and post-CMOS technologies. Nanoelectronics refers to the possible future technologies beyond conventional CMOS scaling limits. This volume addresses the current state-of-the-art nanoelectronic technologies and presents potential options for next-generation integrated circuits. Nanoelectronics for Next-generation Integrated Circuits is a useful reference guide for researchers, engineers, and advanced students working on the frontier of the design and modeling of nanoelectronic devices and their integration aspects with future CMOS circuits. This comprehensive volume eloquently presents the design methodologies for spintronics memories, quantum-dot cellular automata, and post-CMOS FETs, including applications in emerging integrated circuit technologies.
Book Synopsis CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies by : Andrei Pavlov
Download or read book CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies written by Andrei Pavlov and published by Springer Science & Business Media. This book was released on 2008-06-01 with total page 203 pages. Available in PDF, EPUB and Kindle. Book excerpt: The monograph will be dedicated to SRAM (memory) design and test issues in nano-scaled technologies by adapting the cell design and chip design considerations to the growing process variations with associated test issues. Purpose: provide process-aware solutions for SRAM design and test challenges.
Book Synopsis Micro and Nanoelectronics Devices, Circuits and Systems by : Trupti Ranjan Lenka
Download or read book Micro and Nanoelectronics Devices, Circuits and Systems written by Trupti Ranjan Lenka and published by Springer Nature. This book was released on 2021-09-09 with total page 496 pages. Available in PDF, EPUB and Kindle. Book excerpt: The book presents select proceedings of the International Conference on Micro and Nanoelectronics Devices, Circuits and Systems (MNDCS-2021). The volume includes cutting-edge research papers in the emerging fields of micro and nanoelectronics devices, circuits, and systems from experts working in these fields over the last decade. The book is a unique collection of chapters from different areas with a common theme and will be immensely useful to academic researchers and practitioners in the industry who work in this field.
Book Synopsis Advances in Computer Communication and Computational Sciences by : Sanjiv K. Bhatia
Download or read book Advances in Computer Communication and Computational Sciences written by Sanjiv K. Bhatia and published by Springer. This book was released on 2018-08-22 with total page 420 pages. Available in PDF, EPUB and Kindle. Book excerpt: The book includes the insights that reflect ‘Advances in Computer and Computational Sciences’ from upcoming researchers and leading academicians across the globe. It contains the high-quality peer-reviewed papers of ‘International Conference on Computer, Communication and Computational Sciences (IC4S 2017), held during 11–12 October, 2017 in Thailand. These papers are arranged in the form of chapters. The content of this book is divided into two volumes that cover variety of topics such as intelligent hardware and software design, advanced communications, intelligent computing techniques, intelligent image processing, and web and informatics. This book helps the perspective readers’ from computer industry and academia to derive the advances of next generation computer and communication technology and shape them into real life applications.
Book Synopsis Analysis of Single-ended 6T SRAM Cell in 90nm CMOS Technology and Implementation of Charge Recycling Memory Architecture by : Chien-Yu Hans Ting
Download or read book Analysis of Single-ended 6T SRAM Cell in 90nm CMOS Technology and Implementation of Charge Recycling Memory Architecture written by Chien-Yu Hans Ting and published by . This book was released on 2007 with total page 184 pages. Available in PDF, EPUB and Kindle. Book excerpt: As CMOS process technology advances into deep sub-micron era, static leakage power becomes an important design consideration for engineers. Static random access memory (SRAM) occupies over 50% of total transistor counts in a SoC design, and therefore it is essential to minimize its stand-by current for low power applications. This thesis presents a single ended input/output 6T SRAM cell with write-assist (WAcell) feature in 90nm CMOS technology. Without the bit-lines being constantly precharged, the static power of a WAcell is reduced by 6.3X using leakage-biased bit-line technique. The minimized subthreshold currents can be collected to build charge pools and used as a power source to help charge bit lines. The proposed write-assist SRAM memory has reduced overall active power by 42% and standby power by 75% compared to traditional SRAM memory. A complete memory design using write-assist WAcell SRAM cell with decoders, write driver and sense amplifiers is also presented in this thesis.
Book Synopsis Energy Efficient and Reliable Embedded Nanoscale SRAM Design by : Bhupendra Singh Reniwal
Download or read book Energy Efficient and Reliable Embedded Nanoscale SRAM Design written by Bhupendra Singh Reniwal and published by CRC Press. This book was released on 2023-11-30 with total page 213 pages. Available in PDF, EPUB and Kindle. Book excerpt: This reference text covers a wide spectrum for designing robust embedded memory and peripheral circuitry. It will serve as a useful text for senior undergraduate and graduate students and professionals in areas including electronics and communications engineering, electrical engineering, mechanical engineering, and aerospace engineering. Discusses low-power design methodologies for static random-access memory (SRAM) Covers radiation-hardened SRAM design for aerospace applications Focuses on various reliability issues that are faced by submicron technologies Exhibits more stable memory topologies Nanoscale technologies unveiled significant challenges to the design of energy- efficient and reliable SRAMs. This reference text investigates the impact of process variation, leakage, aging, soft errors and related reliability issues in embedded memory and periphery circuitry. The text adopts a unique way to explain the SRAM bitcell, array design, and analysis of its design parameters to meet the sub-nano-regime challenges for complementary metal-oxide semiconductor devices. It comprehensively covers low- power-design methodologies for SRAM, exhibits more stable memory topologies, and radiation-hardened SRAM design for aerospace applications. Every chapter includes a glossary, highlights, a question bank, and problems. The text will serve as a useful text for senior undergraduate students, graduate students, and professionals in areas including electronics and communications engineering, electrical engineering, mechanical engineering, and aerospace engineering. Discussing comprehensive studies of variability-induced failure mechanism in sense amplifiers and power, delay, and read yield trade-offs, this reference text will serve as a useful text for senior undergraduate, graduate students, and professionals in areas including electronics and communications engineering, electrical engineering, mechanical engineering, and aerospace engineering. It covers the development of robust SRAMs, well suited for low-power multi-core processors for wireless sensors node, battery-operated portable devices, personal health care assistants, and smart Internet of Things applications.
Book Synopsis Ultra Low-power Fault-tolerant SRAM Design in 90nm CMOS Technology by :
Download or read book Ultra Low-power Fault-tolerant SRAM Design in 90nm CMOS Technology written by and published by . This book was released on 2007 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: With the increment of mobile, biomedical and space applications, digital systems with low-power consumption are required. As a main part in digital systems, low-power memories are especially desired. Reducing the power supply voltages to sub-threshold region is one of the effective approaches for ultra low-power applications. However, the reduced Static Noise Margin (SNM) of Static Random Access Memory (SRAM) imposes great challenges to the subthreshold SRAM design. The conventional 6-transistor SRAM cell does not function properly at sub-threshold supply voltage range because it has no enough noise margin for reliable operation. In order to achieve ultra low-power at sub-threshold operation, previous research work has demonstrated that the read and write decoupled scheme is a good solution to the reduced SNM problem. A Dual Interlocked Storage Cell (DICE) based SRAM cell was proposed to eliminate the drawback of conventional DICE cell during read operation. This cell can mitigate the singleevent effects, improve the stability and also maintain the low-power characteristic of subthreshold SRAM, In order to make the proposed SRAM cell work under different power supply voltages from 0.3 V to 0.6 V, an improved replica sense scheme was applied to produce a reference control signal, with which the optimal read time could be achieved. In this thesis, a 2K~8 bits SRAM test chip was designed, simulated and fabricated in 90nm CMOS technology provided by ST Microelectronics. Simulation results suggest that the operating frequency at VDD = 0.3 V is up to 4.7 MHz with power dissipation 6.0 ÊW, while it is 45.5 MHz at VDD = 0.6 V dissipating 140 ÊW. However, the area occupied by a single cell is larger than that by conventional SRAM due to additional transistors used. The main contribution of this thesis project is that we proposed a new design that could simultaneously solve the ultra low-power and radiation-tolerance problem in large capacity memory design.
Book Synopsis Emerging Trends in Photonics, Signal Processing and Communication Engineering by : Govind R. Kadambi
Download or read book Emerging Trends in Photonics, Signal Processing and Communication Engineering written by Govind R. Kadambi and published by Springer Nature. This book was released on 2020-04-20 with total page 244 pages. Available in PDF, EPUB and Kindle. Book excerpt: This volumes presents select papers presented during the International Conference on Photonics, Communication and Signal Processing Technologies held in Bangalore from July 18th to 20th, 2018. The research papers highlight analytical formulation, solution, simulation, algorithm development, experimental research, and experimental investigations in the broad domains of photonics, signal processing and communication technologies. This volume will be of interest to researchers working in the field.
