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Author : 張力仁
Publisher :
ISBN 13 :
Total Pages : 115 pages
Book Rating : 4.:/5 (114 download)
Download or read book A 12-bit 10-MS/s Calibration-Free Successive-Approximation Analog-to-Digital Converter written by 張力仁 and published by . This book was released on 2019 with total page 115 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Author : Wei Li
Publisher :
ISBN 13 :
Total Pages : 73 pages
Book Rating : 4.:/5 (874 download)
Download or read book Low-power Successive Approximation Analog to Digital Converter with Digital Calibration written by Wei Li and published by . This book was released on 2014 with total page 73 pages. Available in PDF, EPUB and Kindle. Book excerpt: IC designers are continuously facing the challenges from reduced CMOS feature sizes and supply voltages. ADCs that deliver satisfactory resolutions/speeds while utilizing the state-of-the-art technologies to save power are in high demand. The analog circuits are more and more assisted by various digital calibration techniques to get boosted performances. This dissertation is focused on a low-power 12-bit 12.5-MS/s successive approximation (SAR) ADC with a couple of calibration schemes. The performances of the proposed SAR ADC are enhanced in two directions. To reduce the power dissipation, a power saving strategy has been proposed. Also, several foreground calibration methods for SAR ADCs have been proposed to reduce power dissipation and enhance conversion accuracy. The design was fabricated in 40nm CMOS technology. Measurement results after calibration showed a SFDR of 82.2 dB, and a THD improvement of 22.5 dB. Finally, two new schemes to realize teraohm on-chip resistance are presented. One of the schemes utilizes a switched-capacitor array, and the other utilizes a switch-capacitor ladder. Using these schemes, large resistances can be fabricated with standard CMOS process in an affordable chip area.
Author : 林葦婷
Publisher :
ISBN 13 :
Total Pages : pages
Book Rating : 4.:/5 (866 download)
Download or read book A Full Range Digital Calibration in 12-bit Successive Approximation Register Analog-to-Digital Converter written by 林葦婷 and published by . This book was released on 2013 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt:
Author : Hae-Seung Lee
Publisher :
ISBN 13 :
Total Pages : 356 pages
Book Rating : 4.:/5 (29 download)
Download or read book Self-calibration Techniques for Successive Approximation Analog-to-digital Converters written by Hae-Seung Lee and published by . This book was released on 1984 with total page 356 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Author : 曾華安
Publisher :
ISBN 13 :
Total Pages : 101 pages
Book Rating : 4.:/5 (114 download)
Download or read book A 12-bit 50-MS/s Time-Interleaved Successive-Approximation Analog-to-Digital Converter written by 曾華安 and published by . This book was released on 2019 with total page 101 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Author : Yi-Long Yu
Publisher :
ISBN 13 : 9781658412636
Total Pages : pages
Book Rating : 4.4/5 (126 download)
Download or read book Statistical Calibration for Two-step Analog-to-digital Conversion written by Yi-Long Yu and published by . This book was released on 2019 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: This thesis describes a two-step, hybrid and reconfigurable data converter using statistical calibration. The two-step analog-to-digital converter (ADC) has a front-end successive-approximation register (SAR) ADC and a back-end time-domain (TD) ADC, which together form a hybrid converter. An inter-stage sample-and-hold amplifier (SHA) doubles the operating speed by allowing the operation to be pipelined. A reconfigurable characteristic allows the converter resolution to be adjusted to be 8, 10 or 12 bits. Digital statistical calibration of ADCs can be implemented without any changes to the analog circuits, which allows it to be compatible with the characteristics of scaled CMOS, allowing potential savings in area and power dissipation. Unfortunately, statistical calibration requires some assumptions about the input density. However, these assumptions are less restrictive in this work than in previous work for two reasons. First, statistical calibration of the mismatch in the front-end capacitor arrays requires only that the input distribution be smooth (instead of requiring that the input be known as in previous work). Also, statistical calibration of inter-stage and back-end errors relies on the assumption that the residue or quantization error from the first stage is uniformly distributed. This residue characteristic holds for many ADC inputs and is intuitively explained in this thesis. To demonstrate the statistical calibration, a prototype ADC is fabricated in 40-nm CMOS technology. In the 12-bit mode at 20 MS/s, the maximum SNDR is 59 dB before calibration and 68 dB after calibration, using 6.2 fJ per conversion-step, excluding the power dissipation required by the calibration and 9.1 fJ per conversion-step including the estimated power dissipation for the calibration.
Author : Weitao Li
Publisher : Springer
ISBN 13 : 3319620126
Total Pages : 181 pages
Book Rating : 4.3/5 (196 download)
Download or read book High-Resolution and High-Speed Integrated CMOS AD Converters for Low-Power Applications written by Weitao Li and published by Springer. This book was released on 2017-08-01 with total page 181 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book is a step-by-step tutorial on how to design a low-power, high-resolution (not less than 12 bit), and high-speed (not less than 200 MSps) integrated CMOS analog-to-digital (AD) converter, to respond to the challenge from the rapid growth of IoT. The discussion includes design techniques on both the system level and the circuit block level. In the architecture level, the power-efficient pipelined AD converter, the hybrid AD converter and the time-interleaved AD converter are described. In the circuit block level, the reference voltage buffer, the opamp, the comparator, and the calibration are presented. Readers designing low-power and high-performance AD converters won’t want to miss this invaluable reference. Provides an in-depth introduction to the newest design techniques for the power-efficient, high-resolution (not less than 12 bit), and high-speed (not less than 200 MSps) AD converter; Presents three types of power-efficient architectures of the high-resolution and high-speed AD converter; Discusses the relevant circuit blocks (i.e., the reference voltage buffer, the opamp, and the comparator) in two aspects, relaxing the requirements and improving the performance.
Author : Shankar Thirunakkarasu
Publisher :
ISBN 13 :
Total Pages : 83 pages
Book Rating : 4.:/5 (898 download)
Download or read book Self-calibration and Digital-trimming of Successive Approximation Analog-to-digital Converters written by Shankar Thirunakkarasu and published by . This book was released on 2014 with total page 83 pages. Available in PDF, EPUB and Kindle. Book excerpt: Several state of the art, monitoring and control systems, such as DC motorcontrollers, power line monitoring and protection systems, instrumentation systems and battery monitors require direct digitization of a high voltage input signals. Analog-to-Digital Converters (ADCs) that can digitize high voltage signals require high linearity and low voltage coefficient capacitors. A built in self-calibration and digital-trim algorithm correcting static mismatches in Capacitive Digital-to-Analog Converter (CDAC) used in Successive Approximation Register Analog to Digital Converters (SARADCs) is proposed. The algorithm uses a dynamic error correction (DEC) capacitor to cancel the static errors occurring in each capacitor of the array as the first step upon power-up and eliminates the need for an extra calibration DAC. Self-trimming is performed digitally during normal ADC operation. The algorithm is implemented on a 14-bit high-voltage input range SAR ADC with integrated dynamic error correction capacitors. The IC is fabricated in 0.6-um high voltage compliant CMOS process, accepting up to 24Vpp differential input signal. The proposed approach achieves 73.32 dB Signal to Noise and Distortion Ratio (SNDR) which is an improvement of 12.03 dB after self-calibration at 400 kS/s sampling rate, consuming 90-mW from a +/-15V supply. The calibration circuitry occupies 28% of the capacitor DAC, and consumes less than 15mW during operation. Measurement results shows that this algorithm reduces INL from as high as 7 LSBs down to 1 LSB and it works even in the presence of larger mismatches exceeding 260 LSBs. Similarly, it reduces DNL errors from 10 LSBs down to 1 LSB. The ADC occupies an active area of 9.76 mm2.
Author : Minghao Hu
Publisher : Infinite Study
ISBN 13 :
Total Pages : 24 pages
Book Rating : 4./5 ( download)
Download or read book On Neutrosophic Extended Triplet LA-hypergroups and Strong Pure LA-semihypergroups written by Minghao Hu and published by Infinite Study. This book was released on with total page 24 pages. Available in PDF, EPUB and Kindle. Book excerpt: We introduce the notions of neutrosophic extended triplet LA-semihypergroup, neutrosophic extended triplet LA-hypergroup, which can reflect some symmetry of hyperoperation and discuss the relationships among them and regular LA-semihypergroups, LA-hypergroups, regular LA-hypergroups. In particular, we introduce the notion of strong pure neutrosophic extended triplet LA-semihypergroup, get some special properties of it and prove the construction theorem about it under the condition of asymmetry. The examples in this paper are all from Python programs.
Author : Kun Yang
Publisher :
ISBN 13 :
Total Pages : 61 pages
Book Rating : 4.:/5 (55 download)
Download or read book A 16 Bit 500KSps Low Power Successive Approximation Analog to Digital Converter written by Kun Yang and published by . This book was released on 2009 with total page 61 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Author : 寸恩澤
Publisher :
ISBN 13 :
Total Pages : 113 pages
Book Rating : 4.:/5 (114 download)
Download or read book A 10-bit 300-MS/s Successive-Approximation Analog-to-Digital Converter with a Pre-amplifier-only Comparator written by 寸恩澤 and published by . This book was released on 2019 with total page 113 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Author :
Publisher :
ISBN 13 :
Total Pages : 0 pages
Book Rating : 4.:/5 (145 download)
Download or read book A 12-bit 100MS/s Successive-Approximation Analog-to-Digital Converter with Digital Error Correction and Correlated-Reversed Switching written by and published by . This book was released on 2023 with total page 0 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Author : 黃聖文
Publisher :
ISBN 13 :
Total Pages : 108 pages
Book Rating : 4.:/5 (123 download)
Download or read book A 14-bit 2-MS/s Successive-Approximation Analog-to-Digital Converter with Tree-Based Reversed Switching and Residue Oversampling written by 黃聖文 and published by . This book was released on 2020 with total page 108 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Author : Christopher Leonidas David
Publisher :
ISBN 13 :
Total Pages : 370 pages
Book Rating : 4.:/5 (891 download)
Download or read book All Digital, Background Calibration for Time-Interleaved and Successive Approximation Register Analog-to-Digital Converters written by Christopher Leonidas David and published by . This book was released on 2010 with total page 370 pages. Available in PDF, EPUB and Kindle. Book excerpt: Abstract: The growth of digital systems underscores the need to convert analog information to the digital domain at high speeds and with great accuracy. Analog-to-Digital Converter (ADC) calibration is often a limiting factor, requiring longer calibration times to achieve higher accuracy. The goal of this dissertation is to perform a fully digital background calibration using an arbitrary input signal for A/D converters. The work presented here adapts the cyclic "Split-ADC" calibration method to the time interleaved (TI) and successive approximation register (SAR) architectures. The TI architecture has three types of linear mismatch errors: offset, gain and aperture time delay. By correcting all three mismatch errors in the digital domain, each converter is capable of operating at the fastest speed allowed by the process technology. The total number of correction parameters required for calibration is dependent on the interleaving ratio, M. To adapt the "Split-ADC" method to a TI system, 2M+1 half-sized converters are required to estimate 3(2M+1) correction parameters. This thesis presents a 4:1 "Split-TI" converter that achieves full convergence in less than 400,000 samples. The SAR architecture employs a binary weight capacitor array to convert analog inputs into digital output codes. Mismatch in the capacitor weights results in non-linear distortion error. By adding redundant bits and dividing the array into individual unit capacitors, the "Split-SAR" method can estimate the mismatch and correct the digital output code. The results from this work show a reduction in the non-linear distortion with the ability to converge in less than 750,000 samples.
Author : Simon Louwsma
Publisher : Springer Science & Business Media
ISBN 13 : 9048197163
Total Pages : 148 pages
Book Rating : 4.0/5 (481 download)
Download or read book Time-interleaved Analog-to-Digital Converters written by Simon Louwsma and published by Springer Science & Business Media. This book was released on 2010-09-08 with total page 148 pages. Available in PDF, EPUB and Kindle. Book excerpt: Time-interleaved Analog-to-Digital Converters describes the research performed on low-power time-interleaved ADCs. A detailed theoretical analysis is made of the time-interleaved Track & Hold, since it must be capable of handling signals in the GHz range with little distortion, and minimal power consumption. Timing calibration is not attractive, therefore design techniques are presented which do not require timing calibration. The design of power efficient sub-ADCs is addressed with a theoretical analysis of a successive approximation converter and a pipeline converter. It turns out that the first can consume about 10 times less power than the latter, and this conclusion is supported by literature. Time-interleaved Analog-to-Digital Converters describes the design of a high performance time-interleaved ADC, with much attention for practical design aspects, aiming at both industry and research. Measurements show best-inclass performance with a sample-rate of 1.8 GS/s, 7.9 ENOBs and a power efficiency of 1 pJ/conversion-step.
Author : 胡桓睿
Publisher :
ISBN 13 :
Total Pages : 134 pages
Book Rating : 4.:/5 (114 download)
Download or read book A 10-bit 600-MS/s 2x-Interleaved Timing-Skew Insensitive Successive-Approximation Analog-to-Digital Converter written by 胡桓睿 and published by . This book was released on 2019 with total page 134 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Author : 廖亦勛
Publisher :
ISBN 13 :
Total Pages : 0 pages
Book Rating : 4.:/5 (139 download)
Download or read book All Digital Calibration for High-resolution Successive-approximation Register Analog-to-digital Converter written by 廖亦勛 and published by . This book was released on 2022 with total page 0 pages. Available in PDF, EPUB and Kindle. Book excerpt:
