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A 100 Ms S 9 Bit 043 Mw Sar Adc With Custom Capacitor Arrayproject Supported By The National High Tech Research And Development Program Of China No 2013aa014101
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Book Synopsis A 100 MS/s 9 Bit 0.43 MW SAR ADC with Custom Capacitor Array*Project Supported by the National High-Tech Research and Development Program of China (No. 2013AA014101). by :
Download or read book A 100 MS/s 9 Bit 0.43 MW SAR ADC with Custom Capacitor Array*Project Supported by the National High-Tech Research and Development Program of China (No. 2013AA014101). written by and published by . This book was released on 2016 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: Abstract: A low power 9 bit 100 MS/s successive approximation register analog-to-digital converter (SAR ADC) with custom capacitor array is presented. A brand-new 3-D MOM unit capacitor is used as the basic capacitor cell of this capacitor array. The unit capacitor has a capacitance of 1 fF. Besides, the advanced capacitor array structure and switch mode decrease the power consumption a lot. To verify the effectiveness of this low power design, the 9 bit 100 MS/s SAR ADC is implemented in TSMC IP9M 65 nm LP CMOS technology. The measurement results demonstrate that this design achieves an effective number of bits (ENOB) of 7.4 bit, a signal-to-noise plus distortion ratio (SNDR) of 46.40 dB and a spurious-free dynamic range (SFDR) of 62.31 dB at 100 MS/s with 1 MHz input. The SAR ADC core occupies an area of 0.030 mm 2 and consumes 0.43 mW under a supply voltage of 1.2 V. The figure of merit (FOM) of the SAR ADC achieves 23.75 fJ/conv.
Book Synopsis A 10 Bit 50 MS/s SAR ADC with Partial Split Capacitor Switching Scheme in 0.18 Μm CMOS*Project Supported by the National Natural Science Foundation of China (No. 61401097). by :
Download or read book A 10 Bit 50 MS/s SAR ADC with Partial Split Capacitor Switching Scheme in 0.18 Μm CMOS*Project Supported by the National Natural Science Foundation of China (No. 61401097). written by and published by . This book was released on 2016 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis A 10 B 50 MS/s Two-stage Pipelined SAR ADC in 180 Nm CMOS*Project Supported by the National Natural Science Foundation of China (Nos. 61234002, 61322405, 61306044, 61376033) and the Opening Project of Science and Technology on Reliability Physics and Application Technology of Electronic Component Laboratory (No. ZHD201302). by :
Download or read book A 10 B 50 MS/s Two-stage Pipelined SAR ADC in 180 Nm CMOS*Project Supported by the National Natural Science Foundation of China (Nos. 61234002, 61322405, 61306044, 61376033) and the Opening Project of Science and Technology on Reliability Physics and Application Technology of Electronic Component Laboratory (No. ZHD201302). written by and published by . This book was released on 2016 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: Abstract: A 10-bit 50 MS/s pipelined SAR ADC is presented which pipelines a 5-bit SAR-based MDAC with a 6-bit SAR ADC. The 1-bit redundancy relaxes the requirement for the sub-ADC decision in accuracy. The SAR-based and "half-gain" MDAC reduce the power consumption and core area. The dynamic comparator and SAR control logic are applied to reduce power consumption. Implemented in 180 nm CMOS, the fabricated ADC achieves 56.04 dB SNDR and 5mW power consumption from 1.8 V power supply at 50 MS/s.
