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A 10 Bit 10msps Pipelined Adc With First Stage Conventional Sar Adc And Second Stage Multi Bit Per Cycle Sar Adc
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Book Synopsis A 10-bit, 10Msps Pipelined ADC with First Stage Conventional SAR ADC and Second Stage Multi-bit Per Cycle SAR ADC by : Paridhi Gulati
Download or read book A 10-bit, 10Msps Pipelined ADC with First Stage Conventional SAR ADC and Second Stage Multi-bit Per Cycle SAR ADC written by Paridhi Gulati and published by . This book was released on 2016 with total page 112 pages. Available in PDF, EPUB and Kindle. Book excerpt: A pipelined ADC is generally used for high speeds and high resolutions in applications where latency is not a major concern. This project involves the design of a 10 bit pipelined ADC with a conventional SAR ADC as stage one. The first stage also has an integrated comparator and amplifier. A dynamic automatic gain control scheme is used for the amplification of the first stage residue voltage. Techniques such as redundancy help in achieving higher speed while bidirectional single side switching helps in reducing power consumption. The second stage is a 3 bit per cycle SAR ADC that makes use of a scaled down version of the voltage supply. The ADC designed in this project makes use of 0.13um CMOS technology and is able to achieve a sampling rate of 10MS/s and ENOB of 9.95.
Book Synopsis A 12-bit, 10 Msps Two Stage SAR-based Pipeline ADC by : Miguel Francisco Gandara
Download or read book A 12-bit, 10 Msps Two Stage SAR-based Pipeline ADC written by Miguel Francisco Gandara and published by . This book was released on 2012 with total page 272 pages. Available in PDF, EPUB and Kindle. Book excerpt: The market for battery powered communications devices has grown significantly in recent years. These devices require a large number of analog to digital converters (ADCs) to transform wireless and other physical data into the digital signals required for digital signal processing elements and micro-processors. For these applications, power efficiency and accuracy are of the utmost importance. Successive approximation register (SAR) ADCs are frequently used in power constrained applications, but their main limitation is their low sampling rate. In this work, a two stage pipelined ADC is presented that attempts to mitigate some of the sampling rate limitations of a SAR while maintaining its power and resolution advantages. Special techniques are used to reduce the overall sampling capacitance required in both SAR stages and to increase the linearity of the multiplying digital to analog converter (MDAC) output. The SAR sampling network, control logic, and MDAC blocks are completely implemented. Ideal components were used for the clocking, comparators, and switches. At the end of this design, a figure of merit of 51 fJ/conversion-step was achieved.
Book Synopsis A 10 B 50 MS/s Two-stage Pipelined SAR ADC in 180 Nm CMOS*Project Supported by the National Natural Science Foundation of China (Nos. 61234002, 61322405, 61306044, 61376033) and the Opening Project of Science and Technology on Reliability Physics and Application Technology of Electronic Component Laboratory (No. ZHD201302). by :
Download or read book A 10 B 50 MS/s Two-stage Pipelined SAR ADC in 180 Nm CMOS*Project Supported by the National Natural Science Foundation of China (Nos. 61234002, 61322405, 61306044, 61376033) and the Opening Project of Science and Technology on Reliability Physics and Application Technology of Electronic Component Laboratory (No. ZHD201302). written by and published by . This book was released on 2016 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: Abstract: A 10-bit 50 MS/s pipelined SAR ADC is presented which pipelines a 5-bit SAR-based MDAC with a 6-bit SAR ADC. The 1-bit redundancy relaxes the requirement for the sub-ADC decision in accuracy. The SAR-based and "half-gain" MDAC reduce the power consumption and core area. The dynamic comparator and SAR control logic are applied to reduce power consumption. Implemented in 180 nm CMOS, the fabricated ADC achieves 56.04 dB SNDR and 5mW power consumption from 1.8 V power supply at 50 MS/s.
Book Synopsis Low-Power High-Speed ADCs for Nanometer CMOS Integration by : Zhiheng Cao
Download or read book Low-Power High-Speed ADCs for Nanometer CMOS Integration written by Zhiheng Cao and published by Springer Science & Business Media. This book was released on 2008-07-15 with total page 95 pages. Available in PDF, EPUB and Kindle. Book excerpt: Low-Power High-Speed ADCs for Nanometer CMOS Integration is about the design and implementation of ADC in nanometer CMOS processes that achieve lower power consumption for a given speed and resolution than previous designs, through architectural and circuit innovations that take advantage of unique features of nanometer CMOS processes. A phase lock loop (PLL) clock multiplier has also been designed using new circuit techniques and successfully tested. 1) A 1.2V, 52mW, 210MS/s 10-bit two-step ADC in 130nm CMOS occupying 0.38mm2. Using offset canceling comparators and capacitor networks implemented with small value interconnect capacitors to replace resistor ladder/multiplexer in conventional sub-ranging ADCs, it achieves 74dB SFDR for 10MHz and 71dB SFDR for 100MHz input. 2) A 32mW, 1.25GS/s 6-bit ADC with 2.5GHz internal clock in 130nm CMOS. A new type of architecture that combines flash and SAR enables the lowest power consumption, 6-bit >1GS/s ADC reported to date. This design can be a drop-in replacement for existing flash ADCs since it does require any post-processing or calibration step and has the same latency as flash. 3) A 0.4ps-rms-jitter (integrated from 3kHz to 300MHz offset for >2.5GHz) 1-3GHz tunable, phase-noise programmable clock-multiplier PLL for generating sampling clock to the SAR ADC. A new loop filter structure enables phase error preamplification to lower PLL in-band noise without increasing loop filter capacitor size.
Book Synopsis High-speed and Low-power Pipelined SAR ADCs with Passive Residue Transfer and Dynamic Amplifier by : Hai Huang (Ph.D.)
Download or read book High-speed and Low-power Pipelined SAR ADCs with Passive Residue Transfer and Dynamic Amplifier written by Hai Huang (Ph.D.) and published by . This book was released on 2017 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: High speed analog to digital converters (ADCs) are critical blocks in wideband wireline and wireless communication systems. This dissertation presents the designs of two high-speed pipelined successive-approximation-register (SAR) ADCs with the passive residue transfer technique and the process, voltage and temperature (PVT) stabilized dynamic amplifier. The passive residue transfer technique can effectively and efficiently replace the bandwidth-limiting residue amplifier in the medium-resolution pipelined SAR ADC. As a result, the time and power consumption associated with residue amplification are mostly removed and the ADC can obtain considerable speed improvement. Although dynamic amplifiers are employed in recent published pipelined SAR ADCs to achieve fast residue amplifications, the gain instability still limits the ADC's conversion accuracy when the supply voltage and ambient temperature varies. A PVT-stabilized dynamic amplifier based on the replica technique is reported to mitigate the gain variation over process, voltage and temperature changes. The first design is an 8 bit 1.2 GS/s pipelined SAR ADC with the passive residue transfer. It also utilizes the 2b-1b/cycle hybrid conversion scheme with an appropriate resolution partition to further enhance the conversion speed. The prototype ADC measured a signal-to-noise plus distortion ratio (SNDR) of 43.7 dB and a spurious-free dynamic range (SFDR) of 58.1 dB for a Nyquist input. The ADC consumes the total power dissipation of 5.0 mW and achieves a Walden FoM of 35 fJ/conversion-step at a sample rate of 1.2 GS/s. Although it is fabricated with a 65 nm process, the prototype ADC still achieves the same conversion speed as prior research works fabricated in a 32 nm process. The PVT-stabilized dynamic amplification technique is experimentally validated by the second ADC which is a 12 bit 330 MS/s pipelined-SAR ADC also in 65 nm CMOS. The maximum measured gain variations are 1.5% and 1.2% for the supply voltage varying from 1.25 V to 1.35 V and the temperature varying from −5 oC to 85 oC, respectively; the corresponding SNDR variations of the ADC are
Book Synopsis Design and Implementation of Radix-3/Radix-2 Based Novel Hybrid SAR ADC in Scaled CMOS Technologies by : Md. Manzur Rahman
Download or read book Design and Implementation of Radix-3/Radix-2 Based Novel Hybrid SAR ADC in Scaled CMOS Technologies written by Md. Manzur Rahman and published by . This book was released on 2017 with total page 292 pages. Available in PDF, EPUB and Kindle. Book excerpt: This thesis focuses on low power and high speed design techniques for successive approximation register (SAR) analog-to-digital converters (ADCs) in nanoscale CMOS technologies. SAR ADCs’ speed is limited by the number of bits of resolution. An N-bit conventional SAR ADC takes N conversion cycles. To speed up the conversion process, we introduce a radix-3 SAR ADC which can compute 1:6 bits per cycle. To our knowledge, it is the first fully programmable and efficiently hardware controlled radix-3 SAR ADC. We had to use two comparators per cycle due to ADC architecture and we proposed a simple calibration scheme for the comparators. Also, as the architecture of the DAC array is completely different from the architecture of conventional radix-2 SAR ADC’s DAC arrays, we came up with an algorithm for calibration of capacitors of the DAC. Low power SAR ADCs face two major challenges especially at high resolutions: (1) increased comparator power to suppress the noise, and (2) increased DAC switching energy due to the large DAC size. Due to our proposed architecture,the radix-3 SAR ADC uses two comparators per cycle and two differential DACs. To improve the comparator’s power efficiency, an efficient and low cost calibration technique has been introduced. It allows a low power and noisy comparator to achieve high signal-to-noise ratio (SNR). To improve the DAC switching energy, we introduced a radix-3/radix-2 based novel hybrid SAR ADC. We use two single ended DACs for radix-3 SAR ADC and these two single ended DACs can be used as one differential DAC for radix-2 SAR ADC. So, overall, we only have a single DAC as conventional radix- 2 SAR ADC. In addition, a monotonic switching technique is adopted for radix-2 search to reduce the DAC capacitor size and hence, to reduce switching power. It can reduce the total number of unit capacitors by four times. Our proposed hybrid SAR ADC can achieve less DAC energy compared to radix-3 and radix-2 SAR ADCs. Also, to utilize technology scaling, we used the minimum capacitor size allowed by thermal noise limitations. To achieve high resolution, we introduced calibration algorithm for the DAC array. As mentioned earlier, the radix-3 SAR ADC offers higher power than conventional radix-2 SAR ADC because of simultaneous use of two comparators. In the proposed hybrid SAR ADC, we will be using radix-3 search for first few MSB bits. So, the resolution required for radix-3 comparators are much larger than the LSB value of 10-bit ADC. By implementing calibration of comparators, we can use low power, high input referred offset and high speed comparators for radix-3 search. Radix-2 search will be used for rest of the bits and the resolution of the radix-2 comparator has to be less than the required LSB value. So, a high power, low input referred offset and high speed comparator is used for radix-2 search. Also, we introduced clock gating for comparators. So, radix-3 comparators will not toggle during radix-2 search and the radix-2 comparators will be inactive during radix-3 search. By using the aforementioned techniques, the overall comparator power is definitely less than a radix-3 SAR ADC and comparable to a conventional radix-2 SAR ADC. A prototype radix-3/radix-2 based hybrid SAR ADC with the proposed technique is designed and fabricated in 40nm CMOS technology. It achieves an SNDR of 56.9 dB and consumes only 0.38 mW power at 30MS/s, leading to a Walden figure of merit of 21.5 fJ/conv-step.
Book Synopsis High-Resolution and High-Speed Integrated CMOS AD Converters for Low-Power Applications by : Weitao Li
Download or read book High-Resolution and High-Speed Integrated CMOS AD Converters for Low-Power Applications written by Weitao Li and published by Springer. This book was released on 2017-08-01 with total page 181 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book is a step-by-step tutorial on how to design a low-power, high-resolution (not less than 12 bit), and high-speed (not less than 200 MSps) integrated CMOS analog-to-digital (AD) converter, to respond to the challenge from the rapid growth of IoT. The discussion includes design techniques on both the system level and the circuit block level. In the architecture level, the power-efficient pipelined AD converter, the hybrid AD converter and the time-interleaved AD converter are described. In the circuit block level, the reference voltage buffer, the opamp, the comparator, and the calibration are presented. Readers designing low-power and high-performance AD converters won’t want to miss this invaluable reference. Provides an in-depth introduction to the newest design techniques for the power-efficient, high-resolution (not less than 12 bit), and high-speed (not less than 200 MSps) AD converter; Presents three types of power-efficient architectures of the high-resolution and high-speed AD converter; Discusses the relevant circuit blocks (i.e., the reference voltage buffer, the opamp, and the comparator) in two aspects, relaxing the requirements and improving the performance.
Book Synopsis Digitally Assisted Pipeline ADCs by : Boris Murmann
Download or read book Digitally Assisted Pipeline ADCs written by Boris Murmann and published by Springer Science & Business Media. This book was released on 2007-05-08 with total page 164 pages. Available in PDF, EPUB and Kindle. Book excerpt: Digitally Assisted Pipeline ADCs: Theory and Implementation explores the opportunity to reduce ADC power dissipation by leveraging digital signal processing capabilities in fine line integrated circuit technology. The described digitally assisted pipelined ADC uses a statistics-based system identification technique as an enabling element to replace precision residue amplifiers with simple open-loop gain stages. The digital compensation of analog circuit distortion eliminates one key factor in the classical noise-speed-linearity constraint loop and thereby enables a significant power reduction. Digitally Assisted Pipeline ADCs: Theory and Implementation describes in detail the implementation and measurement results of a 12-bit, 75-MSample/sec proof-of-concept prototype. The Experimental converter achieves power savings greater than 60% over conventional implementations. Digitally Assisted Pipeline ADCs: Theory and Implementation will be of interest to researchers and professionals interested in advances of state-of-the-art in A/D conversion techniques.
Book Synopsis A Low-power, Low-area 10-bit SAR ADC with Length-based Capacitive DAC by : Zhili Pan
Download or read book A Low-power, Low-area 10-bit SAR ADC with Length-based Capacitive DAC written by Zhili Pan and published by . This book was released on 2022 with total page 0 pages. Available in PDF, EPUB and Kindle. Book excerpt: A 2.5 V single-ended 10-bit successive-approximation-register analog-to-digital converter (SAR ADC) based on the TSMC 65 nm CMOS process is designed with the goal of achieving low power consumption (33.63 pJ/sample) and small area (2874 μm2 ). It utilizes a novel length-based capacitive digital-to-analog converter (CDAC) layout to achieve low total capacitance for power efficiency, and a custom static asynchronous logic to free the dependence on a high-frequency external clock source. Two test chips have been designed and the problems found through testing the first chip are analyzed. Multiple improved versions of the ADC with minor variations are implemented on the second test chip for performance evaluation, and the test method is explained.
Book Synopsis Data Conversion Handbook by : Walt Kester
Download or read book Data Conversion Handbook written by Walt Kester and published by Newnes. This book was released on 2005 with total page 977 pages. Available in PDF, EPUB and Kindle. Book excerpt: This complete update of a classic handbook originally created by Analog Devices and never previously published offers the most complete and up-to-date reference available on data conversion, from the world authority on the subject. It describes in depth the theory behind and the practical design of data conversion circuits. It describes the different architectures used in A/D and D/A converters - including many advances that have been made in this technology in recent years - and provides guidelines on which types are best suited for particular applications. It covers error characterization and testing specifications, essential design information that is difficult to find elsewhere. The book also contains a wealth of practical application circuits for interfacing and supporting A/D and D/A converters within an electronic system. In short, everything an electronics engineer needs to know about data converters can be found in this volume, making it an indispensable reference with broad appeal. The accompanying CD-ROM provides software tools for testing and analyzing data converters as well as a searchable pdf version of the text. * brings together a huge amount of information impossible to locate elsewhere. * many recent advances in converter technology simply aren't covered in any other book. * a must-have design reference for any electronics design engineer or technician
Book Synopsis Pipelined ADC Design and Enhancement Techniques by : Imran Ahmed
Download or read book Pipelined ADC Design and Enhancement Techniques written by Imran Ahmed and published by Springer Science & Business Media. This book was released on 2010-03-10 with total page 225 pages. Available in PDF, EPUB and Kindle. Book excerpt: Pipelined ADCs have seen phenomenal improvements in performance over the last few years. As such, when designing a pipelined ADC a clear understanding of the design tradeoffs, and state of the art techniques is required to implement today's high performance low power ADCs.
Book Synopsis Fully-passive Switched-capacitor Techniques for High Performance SAR ADC Design by : Wenjuan Guo (Ph. D. in electrical and computer engineering)
Download or read book Fully-passive Switched-capacitor Techniques for High Performance SAR ADC Design written by Wenjuan Guo (Ph. D. in electrical and computer engineering) and published by . This book was released on 2016 with total page 208 pages. Available in PDF, EPUB and Kindle. Book excerpt: In recent years, SAR ADC becomes more and more popular in various low-power applications such as wireless sensors and low energy radios due to its circuit simplicity, high power efficiency, and scaling compatibility. However, its speed is limited by its successive approximation procedures and its power efficiency greatly reduces with the ADC resolution going beyond 10 bit. To address these issues, this thesis proposes to embed two techniques: 1) compressive sensing (CS) and 2) noise shaping (NS) to a conventional SAR ADC. The realization of both techniques are based on fully-passive switched-capacitor techniques. CS is a recently emerging sampling paradigm, stating that the sparsity of a signal can be exploited to reduce the ADC sampling rate below the Nyquist rate. Different from conventional CS frameworks which require dedicated analog CS encoders, this thesis proposes a fully-passive CS-SAR ADC architecture which only requires minor modification to a conventional SAR ADC. Two chips are fabricated in a 0.13 [micrometer] process to prove the concept. One chip is a single-channel CS-SAR ADC which can reduce the ADC conversion rate by 4 times, thus reducing the ADC power by 4 times. In many wireless sensing applications, multiple ADCs are commonly required to sense multi-channel signals such as multi-lead ECG sensing and parallel neural recording. Therefore, the other chip is a multi-channel CS-SAR ADC which can simultaneously convert 4-channel signals with a sampling rate of one channel's Nyquist rate. At 0.8 V and 1 MS/s both chips achieve an effective Walden FoM of around 5 fJ/conversion-step. This thesis also proposes a novel NS SAR ADC architecture that is simple, robust and low power for high-resolution applications. Compared to conventional [Delta Sigma] ADCs, it replaces the power-hungry active integrator with a passive integrator which only requires one switch and two capacitors. Compared to previous 1st-order NS SAR ADC works, it achieves the best NS performance and can be easily extended to 2nd-order. A 1st-order 10-bit NS SAR ADC is fabricated in a 0.13 [micrometer] process. Through NS, SNDR increases by 6 dB with OSR doubled, achieving a 12- bit ENOB at OSR = 8. An improved version of a 2nd-order 9-bit NS SAR ADC is designed and simulated in a 40 nm process. The SNDR increases by 10 dB with OSR doubled, achieving a 14-bit ENOB at OSR = 16. At a bandwidth of 312.5 kHz, the Schreier FoM is 181 dB and the Walden FoM is 12.5 fJ/conversion-step, proving that the proposed NS SAR ADC architecture can achieve high resolution and high power efficiency simultaneously.
Book Synopsis A 10-Bit 50-MS/s SAR ADC for Dual-Voltage Domain Portable Systems by :
Download or read book A 10-Bit 50-MS/s SAR ADC for Dual-Voltage Domain Portable Systems written by and published by . This book was released on 2015 with total page 104 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis Software-Defined Radio for Engineers by : Alexander M. Wyglinski
Download or read book Software-Defined Radio for Engineers written by Alexander M. Wyglinski and published by Artech House. This book was released on 2018-04-30 with total page 375 pages. Available in PDF, EPUB and Kindle. Book excerpt: Based on the popular Artech House classic, Digital Communication Systems Engineering with Software-Defined Radio, this book provides a practical approach to quickly learning the software-defined radio (SDR) concepts needed for work in the field. This up-to-date volume guides readers on how to quickly prototype wireless designs using SDR for real-world testing and experimentation. This book explores advanced wireless communication techniques such as OFDM, LTE, WLA, and hardware targeting. Readers will gain an understanding of the core concepts behind wireless hardware, such as the radio frequency front-end, analog-to-digital and digital-to-analog converters, as well as various processing technologies. Moreover, this volume includes chapters on timing estimation, matched filtering, frame synchronization message decoding, and source coding. The orthogonal frequency division multiplexing is explained and details about HDL code generation and deployment are provided. The book concludes with coverage of the WLAN toolbox with OFDM beacon reception and the LTE toolbox with downlink reception. Multiple case studies are provided throughout the book. Both MATLAB and Simulink source code are included to assist readers with their projects in the field.
Book Synopsis Pipeline ADC Design Methodology by : Hui Zhao
Download or read book Pipeline ADC Design Methodology written by Hui Zhao and published by . This book was released on 2012 with total page 123 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis A 10-bit 250-MS/s Hybrid SAR ADC with Sub-ranging Concept by :
Download or read book A 10-bit 250-MS/s Hybrid SAR ADC with Sub-ranging Concept written by and published by . This book was released on 2023 with total page 0 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis Investigation of 10-bit SAR ADC Using Flip-flip Bypass Circuit by : Robert Alexander Fontaine
Download or read book Investigation of 10-bit SAR ADC Using Flip-flip Bypass Circuit written by Robert Alexander Fontaine and published by . This book was released on 2013 with total page 98 pages. Available in PDF, EPUB and Kindle. Book excerpt: The Successive Approximation Register (SAR) Analog to Digital Converter (ADC) is power efficient and operates at moderate resolution. However, the conversion speed is limited by settling time and control logic constraints. This report investigates a flip-flop bypass technique to reduce the required conversion time. A conventional design and flip-flop bypass design are simulated using a 0.18[micrometer] CMOS process. Background and design of the control logic, comparator, capacitive array, and switches for implementing the SAR ADCs is presented with the emphasis on optimizing for conversion speed.
