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A 10 Bit 100 Ks S Low Power Sar Adc With Lsb Boosted Technique
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Book Synopsis A 10-bit 100-kS/s Low Power SAR ADC with LSB Boosted Technique by :
Download or read book A 10-bit 100-kS/s Low Power SAR ADC with LSB Boosted Technique written by and published by . This book was released on 2015 with total page 106 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis A 10-bit 100-kS/s Low Power SAR ADC with Time-based Fixed Window by : 何政勳
Download or read book A 10-bit 100-kS/s Low Power SAR ADC with Time-based Fixed Window written by 何政勳 and published by . This book was released on 2012 with total page 97 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis Charge-Sharing SAR ADCs for Low-Voltage Low-Power Applications by : Taimur Rabuske
Download or read book Charge-Sharing SAR ADCs for Low-Voltage Low-Power Applications written by Taimur Rabuske and published by Springer. This book was released on 2016-08-02 with total page 173 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book introduces readers to the potential of charge-sharing (CS) successive approximation register (SAR) analog-to-digital converters (ADCs), while providing extensive analysis of the factors that limit the performance of the CS topology. The authors present guidelines and useful techniques for mitigating the limitations of the architecture, while focusing on the implementation under restricted power budgets and voltage supplies.
Book Synopsis Low-Power High-Speed ADCs for Nanometer CMOS Integration by : Zhiheng Cao
Download or read book Low-Power High-Speed ADCs for Nanometer CMOS Integration written by Zhiheng Cao and published by Springer Science & Business Media. This book was released on 2008-07-15 with total page 95 pages. Available in PDF, EPUB and Kindle. Book excerpt: Low-Power High-Speed ADCs for Nanometer CMOS Integration is about the design and implementation of ADC in nanometer CMOS processes that achieve lower power consumption for a given speed and resolution than previous designs, through architectural and circuit innovations that take advantage of unique features of nanometer CMOS processes. A phase lock loop (PLL) clock multiplier has also been designed using new circuit techniques and successfully tested. 1) A 1.2V, 52mW, 210MS/s 10-bit two-step ADC in 130nm CMOS occupying 0.38mm2. Using offset canceling comparators and capacitor networks implemented with small value interconnect capacitors to replace resistor ladder/multiplexer in conventional sub-ranging ADCs, it achieves 74dB SFDR for 10MHz and 71dB SFDR for 100MHz input. 2) A 32mW, 1.25GS/s 6-bit ADC with 2.5GHz internal clock in 130nm CMOS. A new type of architecture that combines flash and SAR enables the lowest power consumption, 6-bit >1GS/s ADC reported to date. This design can be a drop-in replacement for existing flash ADCs since it does require any post-processing or calibration step and has the same latency as flash. 3) A 0.4ps-rms-jitter (integrated from 3kHz to 300MHz offset for >2.5GHz) 1-3GHz tunable, phase-noise programmable clock-multiplier PLL for generating sampling clock to the SAR ADC. A new loop filter structure enables phase error preamplification to lower PLL in-band noise without increasing loop filter capacitor size.
Book Synopsis A Low-power, Low-area 10-bit SAR ADC with Length-based Capacitive DAC by : Zhili Pan
Download or read book A Low-power, Low-area 10-bit SAR ADC with Length-based Capacitive DAC written by Zhili Pan and published by . This book was released on 2022 with total page 0 pages. Available in PDF, EPUB and Kindle. Book excerpt: A 2.5 V single-ended 10-bit successive-approximation-register analog-to-digital converter (SAR ADC) based on the TSMC 65 nm CMOS process is designed with the goal of achieving low power consumption (33.63 pJ/sample) and small area (2874 μm2 ). It utilizes a novel length-based capacitive digital-to-analog converter (CDAC) layout to achieve low total capacitance for power efficiency, and a custom static asynchronous logic to free the dependence on a high-frequency external clock source. Two test chips have been designed and the problems found through testing the first chip are analyzed. Multiple improved versions of the ADC with minor variations are implemented on the second test chip for performance evaluation, and the test method is explained.
Book Synopsis Design and Implementation of Radix-3/Radix-2 Based Novel Hybrid SAR ADC in Scaled CMOS Technologies by : Md. Manzur Rahman
Download or read book Design and Implementation of Radix-3/Radix-2 Based Novel Hybrid SAR ADC in Scaled CMOS Technologies written by Md. Manzur Rahman and published by . This book was released on 2017 with total page 292 pages. Available in PDF, EPUB and Kindle. Book excerpt: This thesis focuses on low power and high speed design techniques for successive approximation register (SAR) analog-to-digital converters (ADCs) in nanoscale CMOS technologies. SAR ADCs’ speed is limited by the number of bits of resolution. An N-bit conventional SAR ADC takes N conversion cycles. To speed up the conversion process, we introduce a radix-3 SAR ADC which can compute 1:6 bits per cycle. To our knowledge, it is the first fully programmable and efficiently hardware controlled radix-3 SAR ADC. We had to use two comparators per cycle due to ADC architecture and we proposed a simple calibration scheme for the comparators. Also, as the architecture of the DAC array is completely different from the architecture of conventional radix-2 SAR ADC’s DAC arrays, we came up with an algorithm for calibration of capacitors of the DAC. Low power SAR ADCs face two major challenges especially at high resolutions: (1) increased comparator power to suppress the noise, and (2) increased DAC switching energy due to the large DAC size. Due to our proposed architecture,the radix-3 SAR ADC uses two comparators per cycle and two differential DACs. To improve the comparator’s power efficiency, an efficient and low cost calibration technique has been introduced. It allows a low power and noisy comparator to achieve high signal-to-noise ratio (SNR). To improve the DAC switching energy, we introduced a radix-3/radix-2 based novel hybrid SAR ADC. We use two single ended DACs for radix-3 SAR ADC and these two single ended DACs can be used as one differential DAC for radix-2 SAR ADC. So, overall, we only have a single DAC as conventional radix- 2 SAR ADC. In addition, a monotonic switching technique is adopted for radix-2 search to reduce the DAC capacitor size and hence, to reduce switching power. It can reduce the total number of unit capacitors by four times. Our proposed hybrid SAR ADC can achieve less DAC energy compared to radix-3 and radix-2 SAR ADCs. Also, to utilize technology scaling, we used the minimum capacitor size allowed by thermal noise limitations. To achieve high resolution, we introduced calibration algorithm for the DAC array. As mentioned earlier, the radix-3 SAR ADC offers higher power than conventional radix-2 SAR ADC because of simultaneous use of two comparators. In the proposed hybrid SAR ADC, we will be using radix-3 search for first few MSB bits. So, the resolution required for radix-3 comparators are much larger than the LSB value of 10-bit ADC. By implementing calibration of comparators, we can use low power, high input referred offset and high speed comparators for radix-3 search. Radix-2 search will be used for rest of the bits and the resolution of the radix-2 comparator has to be less than the required LSB value. So, a high power, low input referred offset and high speed comparator is used for radix-2 search. Also, we introduced clock gating for comparators. So, radix-3 comparators will not toggle during radix-2 search and the radix-2 comparators will be inactive during radix-3 search. By using the aforementioned techniques, the overall comparator power is definitely less than a radix-3 SAR ADC and comparable to a conventional radix-2 SAR ADC. A prototype radix-3/radix-2 based hybrid SAR ADC with the proposed technique is designed and fabricated in 40nm CMOS technology. It achieves an SNDR of 56.9 dB and consumes only 0.38 mW power at 30MS/s, leading to a Walden figure of merit of 21.5 fJ/conv-step.
Book Synopsis A Low Energy Consumption 10-Bit 100kS/s SAR ADC with Time-based Adaptive Window by : 孔致遠
Download or read book A Low Energy Consumption 10-Bit 100kS/s SAR ADC with Time-based Adaptive Window written by 孔致遠 and published by . This book was released on 2018 with total page 114 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis A 10-bit 27-MS/s Low Power SAR ADC by : 楊孟法
Download or read book A 10-bit 27-MS/s Low Power SAR ADC written by 楊孟法 and published by . This book was released on 2010 with total page 144 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis Fully-passive Switched-capacitor Techniques for High Performance SAR ADC Design by : Wenjuan Guo (Ph. D. in electrical and computer engineering)
Download or read book Fully-passive Switched-capacitor Techniques for High Performance SAR ADC Design written by Wenjuan Guo (Ph. D. in electrical and computer engineering) and published by . This book was released on 2016 with total page 208 pages. Available in PDF, EPUB and Kindle. Book excerpt: In recent years, SAR ADC becomes more and more popular in various low-power applications such as wireless sensors and low energy radios due to its circuit simplicity, high power efficiency, and scaling compatibility. However, its speed is limited by its successive approximation procedures and its power efficiency greatly reduces with the ADC resolution going beyond 10 bit. To address these issues, this thesis proposes to embed two techniques: 1) compressive sensing (CS) and 2) noise shaping (NS) to a conventional SAR ADC. The realization of both techniques are based on fully-passive switched-capacitor techniques. CS is a recently emerging sampling paradigm, stating that the sparsity of a signal can be exploited to reduce the ADC sampling rate below the Nyquist rate. Different from conventional CS frameworks which require dedicated analog CS encoders, this thesis proposes a fully-passive CS-SAR ADC architecture which only requires minor modification to a conventional SAR ADC. Two chips are fabricated in a 0.13 [micrometer] process to prove the concept. One chip is a single-channel CS-SAR ADC which can reduce the ADC conversion rate by 4 times, thus reducing the ADC power by 4 times. In many wireless sensing applications, multiple ADCs are commonly required to sense multi-channel signals such as multi-lead ECG sensing and parallel neural recording. Therefore, the other chip is a multi-channel CS-SAR ADC which can simultaneously convert 4-channel signals with a sampling rate of one channel's Nyquist rate. At 0.8 V and 1 MS/s both chips achieve an effective Walden FoM of around 5 fJ/conversion-step. This thesis also proposes a novel NS SAR ADC architecture that is simple, robust and low power for high-resolution applications. Compared to conventional [Delta Sigma] ADCs, it replaces the power-hungry active integrator with a passive integrator which only requires one switch and two capacitors. Compared to previous 1st-order NS SAR ADC works, it achieves the best NS performance and can be easily extended to 2nd-order. A 1st-order 10-bit NS SAR ADC is fabricated in a 0.13 [micrometer] process. Through NS, SNDR increases by 6 dB with OSR doubled, achieving a 12- bit ENOB at OSR = 8. An improved version of a 2nd-order 9-bit NS SAR ADC is designed and simulated in a 40 nm process. The SNDR increases by 10 dB with OSR doubled, achieving a 14-bit ENOB at OSR = 16. At a bandwidth of 312.5 kHz, the Schreier FoM is 181 dB and the Walden FoM is 12.5 fJ/conversion-step, proving that the proposed NS SAR ADC architecture can achieve high resolution and high power efficiency simultaneously.
Book Synopsis Implementation of a 10-bit A-SAR ADC Circuit Based on Voltage to Time Conversion by : Suresh Koyada
Download or read book Implementation of a 10-bit A-SAR ADC Circuit Based on Voltage to Time Conversion written by Suresh Koyada and published by . This book was released on 2016 with total page 176 pages. Available in PDF, EPUB and Kindle. Book excerpt: Comparators are widely used in analog to digital converters. However, the scaling of CMOS technologies makes the design of low power voltage comparators difficult. In order to overcome this problem time-based comparators are introduced which are suitable for nanometer CMOS technology and low supply voltages. This thesis presents the transistor level implementation of a 10-bit time-based accelerated SAR ADC with a supply voltage of 0.5 V. The design increases the conversion speed compared to conventional SAR ADC by updating the upper bound and lower bound of the search space more aggressively. Various design issues, including optimal switch design, glitch minimization at the charge scaling capacitor array output are discussed. This design achieves a SNDR of 58.78dB at a sampling rate of 90.9kS/s and ENOB (effective number of bits) of 9.47 bits with a power consumption of 280nW.
Book Synopsis A Low Power 10-Bit SAR ADC with DT-MOS at Ultra-Low Supply Voltage by : 簡豪廷
Download or read book A Low Power 10-Bit SAR ADC with DT-MOS at Ultra-Low Supply Voltage written by 簡豪廷 and published by . This book was released on 2018 with total page 97 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Book Synopsis A 0.5-V 9.3-ENOB 68-nW 10-kS/s SAR ADC in 0.18-μm CMOS for Biomedical Applications by :
Download or read book A 0.5-V 9.3-ENOB 68-nW 10-kS/s SAR ADC in 0.18-μm CMOS for Biomedical Applications written by and published by . This book was released on 2017 with total page pages. Available in PDF, EPUB and Kindle. Book excerpt: Abstract: This paper presents a 10-bit ultra-low power successive approximation register (SAR) analog-to-digital converter (ADC) intended for use in wearable biomedical circuits. In order to achieve the nanowatt range power consumption, an energy-efficiency modified VCM -based switching scheme is proposed. In addition, a fully dynamic comparator and a dynamic register are used to eliminate the static power consumption. To improve the signal linearity in such a low supply voltage, a double-boost bootstrapped switch is proposed. A prototype of the proposed SAR ADC was fabricated in 0.18 μm 1P6M CMOS technology within a bio-sensor front-end circuit, which occupies an active area of 370×390 μm 2 . The SAR ADC achieves 57.8 dB SNDR and consumes 68nW at 0.5 V supply voltage and 10 kHz sampling rate, resulting in a figure-of-merits (FOM) of 10.8fJ/conversion-step.
Book Synopsis A Study of SAR ADC and Implementation of 10-bit Asynchronous Design by : Olga Kardonik
Download or read book A Study of SAR ADC and Implementation of 10-bit Asynchronous Design written by Olga Kardonik and published by . This book was released on 2013 with total page 126 pages. Available in PDF, EPUB and Kindle. Book excerpt: Successive Approximation Register (SAR) Analog-to-Digital Converters (ADCs) achieve low power consumption due to its simple architecture based on dominant digital content. SAR ADCs do not require an op-amp, so they are advantageous in CMOS technology scaling. The architecture is often the best choice for battery-powered or mobile applications which need medium resolution (8-12 bits), medium speed (10 - 100 MS/s) and require low-power consumption and small form factor. This work studies the architecture in depth, highlighting its main constraints and tradeoffs involving into SAR ADC design. The work researches asynchronous operation of SAR logic and investigates the latest trends for ADC's analog components - comparator and DAC. 10-bit asynchronous SAR ADC is implemented in CMOS 0.18 μm. Design's noise and power are presented as a breakdown among components.
Book Synopsis Pipeline ADC Design Methodology by : Hui Zhao
Download or read book Pipeline ADC Design Methodology written by Hui Zhao and published by . This book was released on 2012 with total page 123 pages. Available in PDF, EPUB and Kindle. Book excerpt:
Author :Arthur H.M. van Roermund Publisher :Springer Science & Business Media ISBN 13 :1461445876 Total Pages :291 pages Book Rating :4.4/5 (614 download)
Book Synopsis Nyquist AD Converters, Sensor Interfaces, and Robustness by : Arthur H.M. van Roermund
Download or read book Nyquist AD Converters, Sensor Interfaces, and Robustness written by Arthur H.M. van Roermund and published by Springer Science & Business Media. This book was released on 2012-11-26 with total page 291 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book is based on the 18 presentations during the 21st workshop on Advances in Analog Circuit Design. Expert designers provide readers with information about a variety of topics at the frontier of analog circuit design, including Nyquist analog-to-digital converters, capacitive sensor interfaces, reliability, variability, and connectivity. This book serves as a valuable reference to the state-of-the-art, for anyone involved in analog circuit research and development.
Book Synopsis Design, Modeling and Testing of Data Converters by : Paolo Carbone
Download or read book Design, Modeling and Testing of Data Converters written by Paolo Carbone and published by Springer Science & Business Media. This book was released on 2013-10-05 with total page 428 pages. Available in PDF, EPUB and Kindle. Book excerpt: This book presents the a scientific discussion of the state-of-the-art techniques and designs for modeling, testing and for the performance analysis of data converters. The focus is put on sustainable data conversion. Sustainability has become a public issue that industries and users can not ignore. Devising environmentally friendly solutions for data conversion designing, modeling and testing is nowadays a requirement that researchers and practitioners must consider in their activities. This book presents the outcome of the IWADC workshop 2011, held in Orvieto, Italy.
Book Synopsis Low-power Wearable Healthcare Sensors by : R. Simon Sherratt
Download or read book Low-power Wearable Healthcare Sensors written by R. Simon Sherratt and published by MDPI. This book was released on 2020-12-29 with total page 146 pages. Available in PDF, EPUB and Kindle. Book excerpt: Advances in technology have produced a range of on-body sensors and smartwatches that can be used to monitor a wearer’s health with the objective to keep the user healthy. However, the real potential of such devices not only lies in monitoring but also in interactive communication with expert-system-based cloud services to offer personalized and real-time healthcare advice that will enable the user to manage their health and, over time, to reduce expensive hospital admissions. To meet this goal, the research challenges for the next generation of wearable healthcare devices include the need to offer a wide range of sensing, computing, communication, and human–computer interaction methods, all within a tiny device with limited resources and electrical power. This Special Issue presents a collection of six papers on a wide range of research developments that highlight the specific challenges in creating the next generation of low-power wearable healthcare sensors.